Xilinx, Inc.

Cradle Technologies, Inc.

Cradle IP, LLC

David A Harrison

Erik P Machnicki

Moshe B Simon

Joshua M Silver

David Chiang

Napoleon W Lee

Jeffrey H Seltzer

Soren T Soe

Nicholas Kucharewski, Jr

Rakesh Singh

Thomas Y Ho

Hua Xue

David C Wyland

Abdul Malik

A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.

Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling

A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.

A multiply accumulate unit ('MAC') that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8&#xd7;8 operations, four 16&#xd7;16 operations, or one 32&#xd7;32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8&#xd7;8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

Method and system for performing parallel integer multiply accumulate operations on packed data

Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.

Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously

A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.

Method for mapping product terms in a complex programmable logic device

A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both 'fast' function blocks (FFBs) and 'high density' function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Method for programming complex PLD having more than one function block

A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformation to place the equation. If the equation still cannot be placed, the weighting function is altered, thereby changing the criteria by which logic portions are assigned to the function blocks. The placement method is then repeated with the altered weighting function.

Programmable logic device placement method utilizing weighting function

A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

Macrocell with product-term cascade and improved flip flop utilization

A process of programming a programmable logic device (PLD) to carry out a specified logic function. The PLD contains three levels of logic implemented as a plurality of functional blocks, each with AND and OR planes, and a programmable interconnect matrix or logic expander carrying out AND logic. After providing such a PLD with specified size constraints and after specifying a logic function, the function is split or factored into subfunctions or factors. A Boolean factorization procedure chooses factors by replacing pairs of product terms in the first factor with their supercube and minimizing the number input terms and product terms required. Subfunctions or factors which are too large can be simplified by combining pairs of inputs in the interconnect matrix. The product terms of a subfunction or factor can be ordered according to the number of input terms they have and assigned to the functional blocks one at a time. Functional blocks which use many inputs or product terms per output can have some of their assigned subfunctions split so as to pack the PLD more densely. Split subfunctions or factors are recombined in the interconnect matrix. After assigning terms to functional blocks and the matrix, they are loaded into the PLD using a device programmer to configure the logic arrays in the PLD.

Growing community of inventors

Cupertino, CA, United States of America

David A Harrison