Apple Inc.

David A Hardell

Michael Jason Giles

Camille Chen

Cyril De La Cropte De Chanterac

Matthew L Semersky

Gary S Thomason

Jaime Tolentino

Huy Le

Yehonatan Perez

Chris A Ligtenberg

Ron Alan Hopkinson

Ihab A Ali

Gavin J Reid

Yehonantan Perez

Examples of the disclosure are directed to methods of managing power of various modules of an electronic device to prevent the voltage of the battery from falling to an undervoltage lockout (UVLO) threshold. In some examples, software operating on the electronic device or an associated electronic device (e.g., a paired electronic device) may assign power budgets to one or more modules, thereby preventing each module from drawing its maximum current capacity and causing the battery's voltage level to fall to the UVLO threshold. In some examples, a pre-UVLO threshold (i.e., a threshold higher than the UVLO threshold) may be used to modify the states of one or more modules to save power as the voltage of the battery approaches the UVLO threshold, but before the device must be fully powered off.

Brownout avoidance

Circuits, methods, and apparatus that react to brownout or near brownout conditions and mitigate complications that may result. Examples may turn off one or more circuits, such as a Wi-Fi transceiver when a brownout condition is reached or neared. Other examples may provide circuits, methods, and apparatus that proactively avoid brownout conditions. These examples may detect that a brownout condition may occur and take steps, such as Wi-Fi traffic shaping, to avoid them. Still further examples may react to brownout or near brownout conditions one or more times, then preemptively act to avoid further brownout conditions.

Traffic shaping to mitigate brownout conditions

Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described.

Methods and apparatus for enhanced coexistence algorithms in wireless systems

A system to eliminate acoustic noise caused by a first Multi-Layer Ceramic Capacitor (MLCC) array positioned on a printed circuit board (PCB) is disclosed. The first MLCC array generates a first vibration responsible for the acoustic noise in response to receiving a varying input voltage. A third MLCC array senses the first vibration and generates a feedback signal. An adaptive filter then uses the feedback signal to generate an output signal that is used by a second MLCC to generate a second vibration that acts as a counter to dampen the first vibration. Because the input voltage signal is varying in time, the adaptive filter continually samples the varying input voltage and the feedback signal to generate the output signal that minimizes the acoustic noise. The second and third MLCC arrays are selectively positioned and oriented on the PCB for optimum performance.

Adaptive vibration damping mechanism to eliminate acoustic noise in electronic systems

A card connector that allows a card to be at least partially coplanar with a logic board is described herein. A system having a card at least partially coplanar with a logic board is also disclosed. A card connector that allows at least one longitudinal plane through the logic board to intersect at least a point of the card is also disclosed. The card may be a memory module.

Board connector

A chip package for a computer system includes a substrate having a first region and a second region on a first surface, at least one die coupled to the first region on the first surface of the substrate and a main logic board coupled to the second region on the first surface of the substrate. By coupling the die and the main logic board on the first surface of the substrate, an overall thickness of the chip package is reduced.

Growing community of inventors

San Jose, CA, United States of America

David A Hardell