W. L. Gore & Associates, Inc.

Cray Research, Inc.

Other

3m Innovative Properties Company

David A Hanson

Mark F Sylvester

Paul J Fischer

David B Noddin

John J Budnaitis

William George Petefish

Edward C Priest

William G Petefish

Dan L Massopust

Steven C Barber

Ken Shintaku

An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Interconnect module with reduced power distribution impedance

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Constraining ring for use in electronic packaging

A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Method for reducing via inductance in an electronic assembly and article

A method for determining a fiducial misregistration of conductive layers of a laminated substrate by providing a plurality of alternatingly disposed dielectric layers and conductive layers. A predetermined area of resistive material is formed as part of at least one conductive layer. Each predetermined area of resistive material is formed at a same corresponding location in each respective conductive layer, and each predetermined area of resistive material has a first end and a second end. A through-via is formed and connected to each predetermined area of resistive material between the first and second ends of each respective predetermined area. A total resistance is determined between the first end and the second end of each predetermined area of resistive material. A first fractional resistance is determined between the first end of each predetermined area of resistive material and the through-via. A second fractional resistance is determined between the second end of each predetermined area of resistive material and the through-via. A fiducial misregistration of each conductive layer with respect to a location of the through-via is determined based on the respective first and second fractional resistances and the respective total resistance for each predetermined area of resistive material.

Electrical means for extracting layer to layer registration

Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

Clock start up stabilization for computer systems

Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse and fine selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.

Growing community of inventors

Altoona, WI, United States of America

David A Hanson