International Business Machines Corporation

David A Grosch

Marc Douglas Knox

Jody John Van Horn

Franco Motika

Paul Steven Zuchowski

Anne Elizabeth Gattiker

Phil Nigh

Brian C Noble

Erik A Nelson

Ann L Swift

Gregory V Miller

Joel Thomas

A method, apparatus and computer program product for testing semiconductor products that combines multiple techniques. Depending on the requirements, different ones of the techniques are emphasized over the other techniques. The testing applies a technique to achieve a higher single defect acceleration parameter at the expense of a second parameter, thus enabling acceleration of defects that require higher voltage or higher temperature than a traditional 'Burn In' can achieve, which defects would otherwise go unaccelerated. The method manages the adaptation of the different techniques, e.g., how it decides to favor one technique over the other, and how it carries out the favoring of one or more particular techniques in a given test situation. Thus, acceleration to defectivity (defect type and quantity) may be tailored in real time by uniquely leveraging the duration spent in a given section of a process flow based on the prevalence of unique defect types.

Diversified exerciser and accelerator

Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns

Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Integrated circuit testing methods using well bias modification

A method for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.

Integrated circuit testing method using well bias modification

An improved technique for testing semi-conductor chips having different types of circuits thereof is provided. The burn-in test includes providing test engines and/or externally applied patterns for each of the different types of circuits, stressing at high temperature and increased voltage, the semi-conductor containing both types of circuits, and running a sequence of patterns on each of said types of circuits simultaneously by the use of the engines for at least one of the types of circuits.

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Burlington, VT, United States of America

David A Grosch