Coherent Logix, Inc.

Microelectronics and Computer Technology Corporation

David A Gibson

Michael B Doerr

Carl S Dobbs

Michael R Trocino

Michael B Solka

William H Hallidy

Craig Michael Chase

John Mark Beardslee

Keith M Bindloss

Kenneth R Faulkner

Sumeer Arya

Uttam Shyamalindu Ghoshal

Dennis J Herrell

Richard D Nelson

Thomas P Dolbear

Colin A MacKay

Curtis Nathan Potter

Robert Travis Smith

Omkarnath R Gupta

Billy M Hargis

Bill Weigler

Craig M Chase

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.

Memory-network processor with programmable optimizations

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric

A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Processing system with interspersed processors and communication elements having improved communication routing

Multiprocessor fabric having configurable communication that is selectively disabled for secure processing

Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configuration

Processing system with interspersed processors and communication elements having improved wormhole routing

Stall propagation in a processing system with interspersed processors and communicaton elements

A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Processing system with interspersed processors using selective data transfer through communication elements

Processing system with interspersed processors and dynamic pathway creation

Processing system with interspersed processors using shared memory of communication elements

Processing system with interspersed processors and communication elements

Growing community of inventors

Austin, TX, United States of America

David A Gibson