International Business Machines Corporation

Xilinx, Inc.

Hitachi Global Storage Technologies Netherlands B.v.

David A Freitas

Kevin Roy Vannorsdel

Mantle Man-Hon Yu

Louis Joseph Serrano

John Thomas Contreras

Shih-Ming Shih

Hsung Jai Im

Paul Wingshing Chung

Kevin Zheng

Westerfield John Ficken

Hayden Cranford

Joseph M Stevens

Klaassen Berend Klaassen

Chorng K Wang

Roomy Khan

Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics

A differential feedback equalizer is described. A differential feedback equalizer comprises a summer circuit configured to receive a differential input signal and a summer tap circuit output and to generate a summer circuit differential output; a first latch configured to receive the summer circuit differential output from the summer circuit and to generate a first differential latch output comprising a first state of the differential feedback equalizer; and a feedback circuit having a NAND gate coupled to an output of the first latch and configured to generate a differential tap feedback signal; wherein the feedback circuit comprises a NAND gate buffer that maintains the differential tap feedback signal at a predetermined voltage during a reset phase of the first latch. A method of implementing a differential feedback equalizer is also described.

Differential feedback equalizer and method of implementing a differential feedback equalizer

A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the Cclocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a Cclock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the Cclocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation.

Implementing power savings in HSS clock-gating circuit

A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Serial link receiver with wide input voltage range and tolerance to high power voltage supply

Magneto-Resistive (MR) head read/write channel () provides timer (), detector () and amplifier () to reduce the amount of time required to transition from read mode to write mode. Controller () issues the write command (WGATE) to signal a pending mode change from read to write mode. While read/write channel () remains in read mode, timer () begins a configurable countdown sequence, which allows Arm Electronics (), except for a final output stage of amplifier (), to power up in preparation for write mode. Once timer () has reached terminal count, signal (CHWGATE) is de-asserted, which causes write channel () to warm up. After warm up, write channel () writes serial data (WRITE DATA) to detector (). Still in read mode, detector () detects the presence of WRITE DATA from write channel () and asserts signal (AEWGATE). The assertion of signal (AEWGATE) cancels read mode and enables amplifier () to source current to MR head () in response to WRITE DATA to begin a fully operational write mode.

Method and apparatus for improved read-to-write transition time for a magneto-resistive head

A method and apparatus for high voltage applications, with the latest MOSFET technology having limited terminal-to-terminal voltage capability, includes a switch circuit having at least two serially coupled MOSFETs and a two-stage MOSFET connection using a plurality of resistors, and/or a bipolar transistor, and a plurality of diodes. One of the high voltage applications is a high speed write driver in a computer disk drive. The switch circuit switches on/off between zero volt and a voltage higher than a maximum terminal-to-terminal voltage of a single MOSFET which is typically five volts. A required voltage in high voltage applications can be in excess of, for example, 8 or 9 volts.

Method and circuitry for high voltage application with MOSFET technology

A method and apparatus for improving baseline recovery of an MR head using a programmable AC coupling pole. The location of the pole may be adjusted to achieve the fastest recovery from a baseline shift without degrading the normal channel performance. Further, the pole may be moved during the data recovery procedure to recover from a data read error. The programmable AC coupling pole includes a circuit path carrying digital data signals read from a recording media by a magnetic head, an amplifier coupled to the circuit path for amplifying the digital data signals, and a recovery time setting device having an programmable recovery time constant associated therewith. Once a data read error has been detected by the system, the recovery time constant may be adjusted to set a recovery time for the amplifier to provide readable data signals. In addition, a digital controller may be coupled to the recovery time setting device for adjusting the recovery time setting device to change the recovery time constants in response to disturbances to the magnetic head. The programmable AC coupling pole may be disposed at the output of the magnetic head preamplifier or it may be before the data channel amplifier.

Method and apparatus for improving baseline recovery of an MR head using a programmable recovery time constant

A recording channel front-end circuit for driving a write element over a transmission line interconnect provides the improved performance during writing of information. In one embodiment, the recording channel front-end circuit includes a voltage-type write driver coupled to the transmission line interconnect and operable to output a write driver signal to the transmission line interconnect and a receiver termination circuit coupling the transmission line interconnect to the write element. The receiver termination circuit may include an impedance matching network operable match a terminal impedance of the write element to be substantially equal to a characteristic impedance of the transmission line interconnect. In another embodiment, the recording channel front-end circuit includes a voltage-type write driver coupled to the transmission line interconnect and operable to output a write driver signal to the transmission line interconnect and a source termination circuit coupling the voltage-type write driver to the transmission line interconnect. The source termination circuit may include an impedance matching circuit operable match a terminal impedance of the voltage-type write driver to be substantially equal to a characteristic impedance of the transmission line interconnect.

Recording channel with voltage-type write driver for use with transmission-line interconnect

An apparatus and method for sensing and reporting connection integrity of a differential transmission line having proper parallel termination is constructed by generating an error signal which indicates that one or both differential input lines are open. The error signal is generated using a voltage comparator having a first and second input in which these inputs are coupled to the first and second ECL signal lines. The first and second input lines are also coupled to a supply voltage by a first and second dynamic impedance such that the input is pulled high when the signal lines are open. The comparator generates an error signal when the input voltages are greater than voltages normally seen on the signal lines indicating the presence of a open transmission line.

Method and apparatus to sense and report connection integrity of a

A method and apparatus for improving baseline recovery of an MR head using a programmable AC coupling pole. The location of the pole may be adjusted to achieve the fastest recovery from a baseline shift without degrading the normal channel performance. Further, the pole may be moved during the data recovery procedure to recover from a data read error. The programmable AC coupling pole includes a circuit path carrying digital data signals read from a recording media by a magnetic head, an amplifier coupled to the circuit path for amplifying the digital data signals, and a recovery time setting means having an programmable recovery time constant associated therewith. Once a data read error has been detected by the system, the recovery time constant may be adjusted to set a recovery time for the amplifier to provide readable data signals. In addition, a digital controller may be coupled to the recovery time setting means for adjusting the recovery time setting means to change the recovery time constants in response to disturbances to the magnetic head. The programmable AC coupling pole may be disposed at the output of the magnetic head preamplifier or it may be before the data channel amplifier.

Method and apparatus for improving baseline recovery of an MR head using

The present invention concerns an apparatus, method, and article of manufacture that satisfies the need for verifying the identity of a designated head in a gang servo head environment by querying a control parameter unit. In one embodiment, the invention may be implemented to provide a method to increase head select robustness for group head systems controlled by drive electronics. The method is practiced when a request is made for a designated head to perform a read or write operation. The request is received by a control parameter unit included in an arm electronics unit. The control parameter unit is then queried to verify the identity of the arm electronics unit selected. The identity of the designated head is then received. A parity check of the control data is performed and, assuming no errors, an actuating arm containing the designated head is positioned. The selected arm electronics unit is loaded with read or write data copied from a host system and transferred to or from the storage device. In various embodiments, the actuating arm electronics unit contain circuitry for repeatedly verifying that the proper head was selected and the integrity of data copied to the arm electronics unit.

Method and apparatus to increase head/AE select robustness for a system

Track information decoding circuitry of a data storage device servo control system decodes binary track information in a readback servo signal by detecting opposite polarity track information pulse pairs so as to produce a track information signal 'one' bit if the presence of an opposite polarity pulse pair is detected and produce a track information signal 'zero' bit in the absence of an opposite polarity pulse pair, wherein a one bit is produced only if there has been detected a second pulse of a readback signal pulse pair having a magnitude greater than a predetermined threshold value and having a correct polarity. The polarity of the last di-bit of the servo signal AGC field can be used to set the polarity in the pulse qualification process. Alternatively, a pulse detecting circuit at disk start-up decodes the readback signal first assuming a positive leading di-bit pulse and then assuming a negative leading di-bit pulse, determines the number of errors associated with each assumption, and selects the di-bit pulse polarity for further decoding that produced the decoded information having fewer errors.

Method and apparatus for servo pulse detection with high AC coupling and

A channel circuit that receives an analog disk readback signal of a data storage disk drive includes a comparator string and a data channel binary decoder that together comprise what is commonly referred to as a flash analog-to-digital (A/D) converter, which processes the data channel information of the readback signal. The servo information of the readback signal is provided to the comparator string of the data channel flash A/D converter, whose output then is provided to a servo burst binary decoder for decoding to produce the desired servo burst data. Thus, the servo information is digitized and decoded at the relatively high speed possible with a flash A/D converter, without requiring a comparator string in addition to what would otherwise be provided for the data channel application.

High speed PES demodulator

Logic for detecting the reliability of an address in Pennington code (PCODE). The address is parsed into two separate halves. The first half corresponds to the front portion of the PCODE address and the second half corresponds to the back portion of the same. The two halves are compared to determine the reliability of the address. If the address is not reliable, a head position estimation is used to position the head over the described track. If the address is reliable, the PCODE is combined with a position error signal to position the head.

Method and apparatus for servo control with error detection of gray

A servo signal demodulator for a banded data disk drive system includes a single data sampling clock for both the data channel sampling and the servo data sampling. The demodulator includes an analog-to-digital converter that receives a readback signal from a read/write head of the disk drive system and generates samples of the readback signal in accordance with a repeating sampling clock signal whose frequency changes as a function of a data band of the disk drive over which the read/write head is positioned, an adder that sums the readback signal samples from the analog-to-digital converter to thereby produce an integrated readback signal value, and a servo signal decoder circuit that latches the adder sum to a register after the adder has summed a sufficient number of readback signal samples to comprise a servo burst, in accordance with a data channel sampling clock signal, and provides demodulated signal information to a servo controller.

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Morgan Hill, CA, United States of America

David A Freitas