Bull Hn Information Systems, Inc.

David A Egolf

Bruce A Noyes

Stefan R Bohult

Chad Farmer

William A Shelly

Wayne R Buzby

David S Edwards

William Lawrance

Donald P Levine

Todd Bradley Kneisel

Michael L Giroux

Arnold S Lipton

David W Wagner

Mariam P Sanford

Anne Marie Wunderlin

Jared A Egolf

Jesse D Hunter

Michel Brown

Jon Keil

Michael Meduna

Eric W Hardesty

A data processing system participating in two-phase transaction processing operations which, when a system failure occurs while one or more transactions are in process, can successfully rebuild 'in-doubt' states even when another system failure occurs during an attempt to effect the rebuild. The system includes a file management system having exclusive access to reserved locations in the memory for reading and writing meta-data therein and physical file access logic selectively coupling the memory and the database access application, the physical file access logic incorporating file protections which are controlled by the file management system; such that, in the event of a failure, the local state of the transaction can be faithfully rebuilt after restart by accessing the meta-data. Upon restart after a failure, the results of incomplete non-'in-doubt' transactions are removed, the files which have been updated by &#x201c;in-doubt&#x201d; transactions are locked and normal access to the affected database is then permitted.

Rebuilding 'in-doubt' states reliably after multiple system failures in a data processing system performing two-phase transaction processing

In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Each Target processor is mapped to a Host thread. When a page fault is detected by the Host operating system, it is checked to see if it belongs to the Target system, and if it does, the executing thread transfers its processor identity to a free thread, and then completes processing the page fault. Upon completion, it marks the processes that had been executing on that thread and processor as available for execution, then blocks until activated. Another thread, upon dispatching that process, wakes up the blocked thread and transfers its processor identity to that thread, which continues to execute the interrupted process.

Method and data processing system for emulating virtual memory utilizing threads

A processor in a data processing system having multiple cache memories performs cache memory or processor module affinity dispatchin. Processes awaiting dispatch are stored in prioritized queues. Each queue has a priority chain, and a chain for each cache memory or processor module, with each chain containing processes ready for dispatch. The dispatcher checks the queues in priority order, starting with the priority chain for a queue, followed by the chain corresponding to the cache memory or processor module that the process last executed upon, followed by chains corresponding to other cache memories or processor modules.

Method and data processing system providing processor affinity dispatching

In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This &ldquo;unfair&rdquo; memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by &ldquo;balking&rdquo; or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

Gate close balking for fair gating in a nonuniform memory architecture data processing system

Gate close failure notification for fair gating in a nonuniform memory architecture data processing system

In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, determining a working space base address for that working space, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address.

Method and data processing system for emulating virtual memory working spaces

A method of addressing mass storage memory in which information is stored in Space Control Pages of physically contiguous disk segments subject to irregularities in the mapping is disclosed. Space Control Pages fall at regular intervals across the address space. An efficient hashing method is disclosed that first hashes record keys across the entire address space to form a hash index. If the hash index falls into one of the Space Control Pages, the key is rehashed across the contiguous hash space following the Space. Control Page utilizing a second hash function. The result of the second hash function is added to the start of the contiguous hash space following the Space Control Page to generate the hash index utilized for those records that initially hashed into a Space Control Page. In all cases the generated hash index is utilized to store and retrieve records in a database or hash file.

Method and data processing system for hashing database record keys in a discontinuous hash table

In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, selecting a working space base address data structure entry utilizing the corresponding working space number, determining a working space base address from that selected working space base address data structure entry, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address. A corresponding working space limit entry can be utilized to bounds check the addresses generated.

Data structure for emulating virtual memory working spaces

A cache manager of a relational database management system (RDBMS) is able to bypass time consuming search operations through the use of a key memory structure and locate generated code segments within an SQL cache within a minimum of time. The SQL cache contains the generated code segments used to execute SQL statements as well as the structures and program logic used for maintaining the cache. The key memory structure is located in an area of memory utilized by the SQL runtime routines in executing applications. The runtime routines provide an interface between the application and the RDBMS.

Method and apparatus for improving the performance of a generated code cache search operation through the use of static key values

When emulating a Target architecture on a Host system having a different architecture, virtual to real address translation is typically expensive in terms of computer cycles. The cost can be significantly reduced by utilizing direct page table pointers to short-circuit the address translation. In a system additionally supporting segments framing portions of virtual memory, the direct page table pointers are associated with segment registers and point to the page table entry corresponding to the first location in a segment. Direct page table pointers are invalidated when underlying virtual memory management tables are modified.

Processor emulation virtual memory address translation

A system and method that enhances the data access performance of a multi-layer relational database manager by expanding the code generation component layer of the database manager to include a number of performance enhancing subroutines designed to execute functions performed by lower component layers substantially faster than if the functions were executed by such lower component layers. Each such subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the processing of a SQL request. During process of generating code for a specific SQL query, the code generation component layer inserts calls to the different performance enhancing subroutines in place of normally included calls to lower component layers. This results in the insertion of the different performance enhancing subroutines into the generated code. Such routines enable the dynamically generated code at query execution time to perform lower component layer functions based on the characteristics of the original query statement resulting in increased performance.

Method and system for dynamically generating code to enhance the performance of a relational database manager that provides access to a relational database

In the emulation of a target system utilizing a multiprocessor ( ) host system ( ) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memory. The old contents of a word ( ) in memory are loaded ( ) into a first register ( ). A loop is then entered. The contents of the first register ( ) are copied ( ) into a second ( ). The contents of the second register ( ) are then appropriately modified ( ), depending on the instruction being emulated. After a lock ( ), the two registers are compare-exchanged ( ) with the memory word ( ), resulting in the modified second register ( ) being written to the memory word ( ) if the contents of the first register ( ) match. Otherwise, the compare-exchange instruction ( ) loads the current copy of the word ( ) into the first register ( ), and the loop repeats.

Different word size multiprocessor emulation

A system and method that enhances the row retrieval performance of a multi-layer relational database manager by including in the code generation component layer of the database manager a row retrieval performance enhancing subroutine designed to execute functions performed by a lower component layer substantially faster than if the functions were executed by such lower component layer. The subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the execution of a SQL request. The output code generated to execute a specific SQL query, including calls to the row retrieval subroutine in place of normally included calls to the lower component layer. This enables the generated code to perform lower component layer functions with specialized code designed to increase performance based on the characteristics of the data being retrieved.

Method and system for using dynamically generated code to perform record management layer functions in a relational database manager

A host system includes a multicache system configured within the host system's memory which has a plurality of local and central cache systems used for storing information being utilized by a plurality of processes running on the system. Persistent shared memory is used to store control structure information entries required for operating central cache systems for substantially long periods of time in conjunction with the local caches established for the processes. Such entries includes a descriptor value for identifying a directory control structure and individual sets of descriptors for identifying a group of control structures defining those components required for operating the configured central cache systems. The cache directory structure is used for defining the name of each configured central cache system and for providing an index value identifying the particular set of descriptors associated therewith. The multicache system also includes a plurality of interfaces for configuring the basic characteristics of both local and central cache systems as a function of the type and performance requirements of application processes being run.

Method and apparatus for improving the performance of a database

Convoys resulting from competing requests for a popular service are detected and dispersed by a scheduling procedure. When a request first enters the procedure, a determination is made as to whether the procedure is currently in the convoy disperse mode. If not, availability of the service is checked, and if it is available, the request is serviced. If the service is not available, a delay is instituted, and availability of the service is checked again. If it is still not available, a wait-for-service count is checked to determine if it exceeds a predetermined value. If not, the present request is sent to a queued wait. If so, the convoy disperse flag is set true, and the request is sent to the queued wait. If the convoy disperse flag was already true when the request was received into the procedure, a different path is taken in which a loop is entered which involves temporarily relinquishing the processor. This loop can be passed through a predetermined number of times with the service availability checked each pass. If the service becomes available, the convoy disperse flag is set false, and the request is serviced. If the service does not become available after the predetermined number of passes through the loop, the request is sent to the queued wait.

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Glendale, AZ, United States of America

David A Egolf