Intersil Americas Inc.

Harris Corporation

Intersil Corporation

David A Decrosta

Michael D Church

John T Gasner

Paul E Bakeman, Jr

Chris A McCarty

Sameer D Parab

Robert Lomenick

Jack H Linn

Robert T Fuller

Robert K Lowry

Michael J Morrison

Howard L Evans

John J Hackenberg

Martin E Walter

Robert Lomenic

Paul E Bakeman

Robert L Lomenick

Paul E Bakeman Jr

A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Active area bonding compatible high current structures

A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

A method of operating a plasma etcher wherein gas is introduced into the etcher at a substantially higher rate than a previous standard rate for a desired etch selectivity, and the throttle valve's open value is set to a substantially greater open value than a previous standard open value for the desired etch selectivity. The method may also include introducing the gas at a lower pressure than the pressure of the previous standard pressure for a desired etch selectivity.

Enhanced plasma etch process

A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Radiation hardened dielectric for EEPROM

A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.

Planarization method by use of particle dispersion and subsequent

A process for removing unwanted contaminant metallic oxide from the surface of a nickel branding layer of an electronic circuit package, in order to enhance the affinity of a layer of phenolic branding ink to the surface of the metallic branding layer involves treating the surface of the metallic branding layer with a hydrogen-containing, chemical reducing gas phase ambient, so that oxygen within the surface oxide chemically combines with the hydrogen component within the ambient, so as to form readily removable water. The surface of the metallic branding layer is thereby substantially free of surface oxide, providing a greater surface area of metallic-ink bonding sites. As a consequently, a subsequently deposited layer of branding ink strongly adheres to the surface of the nickel and is not readily removed during further cleaning of the circuit package.

Growing community of inventors

Melbourne, FL, United States of America

David A Decrosta