Mips Technologies, Inc.

David A Courtright

Ryan C Kinter

G Michael Uhler

Kevin D Kissell

Radhika Thekkath

Darren Miller Jones

Lawrence Henry Hudepohl

Vidya Rajagopalan

Lavi A Lev

John B Knowles

A method, cache controller, and computer processor provide a parallel mapping system whereby a plurality of mappers processes several inputs simultaneously. The plurality of mappers are disposed in a pipelined processor upstream from a multiplexor. Mapping, tag comparison, and selection by the multiplexor all occur in a single pipeline stage. Data does not wait idly to be selected by the multiplexor. Instead, each instruction of a first instruction set is read in parallel into a corresponding one of the plurality of mappers. This parallel mapping system implementation reduces processor cycle time and results in improved processor efficiency.

Mapping system and method for instruction set processing

A Web-based integrated circuit design system, method and computer program product tool allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The services and data include competing standard architectures and reference designs. The integrated circuit design tool allows users (e.g., design engineers) to efficiently design cores and systems-on-a-chip (SOCs). The integrated circuit design tool is a &ldquo;virtual lab&rdquo; which allows and aides design engineers at every stage of IC product design&mdash;architecture choice, implementation options, software development, and hardware design.

System, method and computer program product for web-based integrated circuit design

An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page. The extended memory attributes index field is a field that is also employed by a legacy memory management protocol to prescribe legacy properties. The plurality of extended attributes registers are initialized to states that correspond to the legacy properties so that the CPU is compatible with operating systems employing the legacy memory management protocol.

Mechanism for extending properties of virtual memory pages by a TLB

An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available.

Scalable on-chip system bus

A low-latency scratchpad RAM memory system is disclosed. The scratchpad RAM memory system can be accessed in parallel to a primary cache. Parallel access to the scratchpad RAM memory can be designed to be independent of a corresponding cache tag RAM, thereby enabling the scratchpad RAM memory to be sized to any specification, independent of the size of the primary cache data RAMs.

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Los Gatos, CA, United States of America

David A Courtright