Texas Instruments Corporation

David A Comisky

Sanjive Agarwala

Charles Lance Fuoco

Iain Craig Robertson

Timothy David Anderson

Christopher L Mobley

Raguram Damodaran

Bradley James Griffis

Joseph R Zbiciak

Keith Balmer

David J Hoyle

Steven D Krueger

John D Keay

Amarjit Singh Bhandal

Merrill Ray Newman

Brandon Christopher Azbell

It is desirable for interrupt handling routines to be aware of the interrupt latency&#x2014;the time between a interrupt request is received and the time when the interrupt service routine begins executing. A method is shown wherein the latency is measured by a dedicated counter and is available to the interrupt service routine. Alternately, a threshold may be set indicating the maximum acceptable latency and the interrupt service routine is signaled when said maximum is reached.

Method of providing timing information for interrupts

Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein includes supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail.

Supervising and sequencing commonly driven power supplies with digital information

A system and method are disclosed to mitigate the interference on DSL due to high frequency components associated with a change in a POTS condition, such as POTS ringing. In response to detecting that a potentially disruptive POTS condition is to about to occur, downstream DSL traffic can be temporarily stopped. The stoppage can include downstream traffic of voice and/or data.

System and method to mitigate pots ringing interference in DSL

A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Transfer request bus node for transfer controller with hub and ports

In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

Active ports in a transfer controller with hub and ports

The transfer controller with hub and ports uses a write allocation counter and algorithm to control data reads from a source port. The write allocation count is the amount of data that can be consumed immediately by the write reservation station of a slow destination port and the channel data router buffers. This is used to throttle fast source port read operations to whole read bursts until space to adsorb the read data is available. This ensures that the source port response queue is not blocked with data that cannot be consumed by the channel data router and the slow destination port. This condition would otherwise block a fast source port from providing data to the other destination ports.

Write allocation counter for transfer controller with hub and ports

A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as a crucial part of the transfer controller. The request queue manager receives these data transfer request packets from plural transfer requests nodes. The request queue manager sorts transfer request packets by their priority level and stores them in the queue manager memory. The request queue manager processes dispatches transfer request packets to a free data channel based upon priority level and first-in-first-out within priority level.

Request queue manager in transfer controller with hub and ports

Data transfer between a master node ( ) and plural memory nodes ( ) follows a synchronous fixed latency loop bus ( ). Each memory node includes bus interface ( ) which passes command, write data, write address, and read data and read address to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. Simultaneously read and write to a single node is prohibited. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data and of incoming write data. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses

The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.

Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor

A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a first-in-first-out fashion at the data source ports. Each data transfer request has a priority level for execution. In effective channel priority processing the priority level assigned to a source port is the greatest priority level of any data transfer request in the corresponding first-in-first-out queue. This techniques prevents a low priority data transfer request at the output of a source port queue from blocking a higher priority data transfer request further back in the queue. Raising the priority of all data transfer requests within a source port queue enables the low priority data transfer request to complete enabling the high priority data transfer request to be reached. Thus both the low priority data transfer request and the high priority data transfer request in the queue of a single port are serviced before intermediate priority data transfer requests at the output of other source port queues.

Effective channel priority processing for transfer controller with hub and ports

This invention enables a program controlled cache state operation on a program designated address range. The program controlled cache state operation could be writeback of data cached from the program designated address range to a higher level memory or such writeback and invalidation of data cached from the program designated address range. A cache operation unit includes a base address register and a word count register loadable by the central processing unit. The program designated address range is from a base address for a number of words of the word count register. In the preferred embodiment the program controlled cache state operation begins upon loading the word count register. The cache operation unit may operate on fractional cache entries by handling misaligned first and last cycles. Alternatively, The cache operation unit may operate only on whole cache entries. The base address register increments and the word count register decrements until when the word count reaches zero.

Programmer initiated cache block operations

The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this invention, parallel size calculation/write annulment decision capability is employed. This technique facilitates the process of setting up complex transfers without risking brute force inefficient processor cycles. Annulment determination allows detection of cases when a set of data cannot be output immediately and the destination pipeline postpones execution of the write command.

Parallel transfer size calculation and annulment determination in transfer controller with hub and ports

An external direct memory access unit includes an event recognizer recognizing plural event types, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized transaction processor. The service request parameters include a priority for centralized transaction processor independent of the event recognition priority. The service request parameters may be stored in the form of a linked list. The service requests are preferably direct memory accesses which may include writes to the parameter memory for self modification. The centralized transaction processor may signal an event to event recognizer upon completion of a requested data transfer.

External direct memory access processor interface to centralized transaction processor

A digital system is provided with a microprocessor ( ), a cache ( ) and various memory and devices ( ). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) ( ). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit ( ) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.

Cache memory controlled by system address properties

A direct memory access function for servicing real-time events, ensures that any parameter reloads occur during times when the direct memory access channel is idle and guarantees completion before the channel begins active operation again. The direct memory access channel whose parameters are to be updated is disabled during the update cycle. This ensures that no requests are processed until the new parameters have been written to the direct memory access channel parameters. A second direct memory access channel may be used to reload the data transfer parameters permitting a self-modifying direct memory access function.

Growing community of inventors

Plano, TX, United States of America

David A Comisky