Texas Instruments Corporation

David A Bell

Che-Chia Wei

Roger A Haken

Thomas C Holloway

Thomas E Tang

Robert H Havemann

A method for fabricating an integrated circuit having a buried doped region is disclosed. A thermal oxide layer is formed over a portion of a p-type substrate at which an n+ buried doped region is not to be formed, masking the implant for the buried doped region. Anneal of the implant is performed in an oxidizing atmosphere, growing further oxide over the surface. The oxide layers are removed, and a p-type blanket implant is performed for isolation purposes and, if desired, to form a p-type buried doped region; the doping concentration of the n+ buried doped region retards diffusion of the boron to the surface thereover. Alternatively, a higher than normal doping level in the substrate can provide sufficient boron for isolation. An epitaxial layer is then grown over the surface, and the n-well is formed by implanting n-type dopant, with the p-well regions masked by a nitride mask; anneal of the n-well is also done in an oxidizing environment, so that consumption of a portion of the n-well by the oxide further planarizes the topography of the device.

Method for forming integrated circuits having buried doped regions

A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.

Local interconnect

A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.

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Dallas, TX, United States of America

David A Bell