Broadcom Corporation

David A Baer

Darren Duane Neuman

Patrick Y Law

Brian Francis Schoner

Jason C Demas

Aleksandr M Movshovich

Brad Albert Delanghe

Steven T Jaffe

Rajesh Mamidwar

Chengfuh Jeffrey Tang

Greg Alan Kranawetter

Sandeep Bhatia

Iue-Shuenn Chen

Francis Cheung

Hoang Nhu

Ut Nguyen

Tracy C Denk

Shawn Val Johnson

James Douglas Sweet

Yao-Hua Tseng

Guang-Ting Shih

Jeffrey S Bauch

Brad Grossman

Chuck Monahan

David Chao Hua Wu

Dan Simon

Sang Van Tran

Thu T Nguyen

Hsien-Chih Jim Tseng

Ben Giese

Lakshman Ramakrishnan

Honman Law

Jeff Tingley

Keith LaRell Klingler

Keith LaRell Klinger

A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Television functionality on a chip

Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

System and method for configuring a display pipeline

Systems and methods that provide graphics using a graphical engine are provided. One such system includes at least one graphical pipeline and a graphical engine. The at least one graphical pipeline is coupled to a bus and operable to generate a plurality of graphical layers. The graphical engine is coupled to the bus and operable to receive, over the bus, the plurality of graphical layers. The graphical engine is operable to composite the received plurality of graphical layers into a composite graphical layer, and to store the composite graphical layer in a local memory of the graphical engine.

System and method for providing graphics using graphical engine

Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Multi-pass system and method supporting multiple streams of video

Systems and methods are disclosed for filter modules in a video display system or network. One embodiment relates to a method for operating a filter module in a video display network comprising determining a picture type, display type and operation of the display network. The method further comprises determining, in real time, a filter configuration from a plurality of possible filter configurations based on the determined picture type, display type and operation.

Filter module for a video decoding system

System and method for configuring a display pipeline using a network

Systems and methods that provide graphics using a graphical engine are provided. In one example, a system may provide layered graphics in a video environment. The system may include a bus, a graphical engine and a graphical pipeline. The graphical engine may be coupled to the bus and may be adapted to composite a plurality of graphical layers into a composite graphical layer. The graphical engine may include a memory that stores the composite graphical layer. The graphical pipeline may be coupled to the bus and may be adapted to transport the composite graphical layer.

System and method for processing data using a network

An integrated receiver with multiple, independently synchronized clock signals for multiple channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. An integrated circuit that services two satellite programs must generate and distribute corresponding time domain clocks to the various components of the integrated circuit. The transport block that receives one or more satellite signals from a demodulating block will extract program clock recover values from each signal being decoded and use these values to produce an error signal or control word that serves as an input to a clock generator. Based upon this input, the clock circuit will produce a corresponding time domain clock for each channel serviced by the integrated circuit. The output of the clock circuit is distributed to the various processing blocks within the integrated circuit that operate upon channel content received and processed by the transport block.

Multiple time-base clock for processing multiple satellite signals

Systems and methods are disclosed for a bus, link or interface. More specifically, systems and methods are discloses for a bus, link or interface adapted to transmit data and control information to at least one processing module and provide synchronization between the data and the control information without requiring the transmission of blank pixels or timing information.

Video bus for a video decoding system

Growing community of inventors

San Jose, CA, United States of America

David A Baer