International Business Machines Corporation

Dave Stephen Levitan

Brian R Konigsburg

Naga P Gorti

Kevin Arthur Chiarot

A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction prediction outcome, and the branch prediction unit. The branch predictor is turned off to save power and avoid miss-predictions when the branch predictor and/or branch prediction unit accuracy is lower than expected.

Adaptive utilization mechanism for a first-line defense branch predictor

A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The IPU may include an address generation unit suitable for generating a set of branch target addresses corresponding to the set of received instructions and a multiplexer configured to receive as inputs the set of branch target addresses. The output of the multiplexer is provided to the instruction address fetch register. The IPU may include an address incrementer suitable for generating a next instruction address corresponding to the next sequential instruction address following the instruction address corresponding to the received set of addresses. In this embodiment, the next instruction address comprises an input to the multiplexer. The IPU may further include selector logic adapted to select the next instruction address as the output of the multiplexer if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The selector logic is adapted to select as the output of the multiplexer the branch target address of the first instruction predicted to be taken if the number of branch instructions in the set of instructions for which branch instruction information must be recorded does not exceed the capacity of IPU to record the branch instruction information in a single cycle.

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Austin, TX, United States of America

Dave Stephen Levitan