Micron Technology Incorporated

Micro Technology, Inc.

Dave Pratt

Raju Ahmed

David A Kewley

Andy Perkins

Frank Speetjens

Yung-Ta Sung

Radhakrishna Kotti

Kyle K Kirby

Yi Hu

Steve Oliver

Mark Hiatt

Gurpreet S Lugani

Siva Naga Sandeep Chalamalasetty

Allen R Gibson

Aaron Kenneth Belsher

Darin Miller

Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

Conductive interconnects and methods of forming conductive interconnects

Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

Assemblies having conductive interconnects which are laterally and vertically offset relative to one another

Assemblies having conductive interconnects which are laterally and vertically offset relative to one another and methods of forming assemblies having conductive interconnects which are laterally and vertically offset relative to one another

Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Methods of forming through substrate interconnects

A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.

Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking

A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.

Die stacking with an annular via having a recessed socket

The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.

Growing community of inventors

Meridian, ID, United States of America

Dave Pratt