Micron Technology Incorporated

Dave Jefferson

Yoshinori Fujiwara

Jason M Johnson

Kevin Gustav Werhane

Vivek Kotti

Toru Ishikawa

Joshua E Alzheimer

Dennis G Montierth

Daniel S Miller

Minoru Someya

C Omar Benitez

Christopher S Wieduwilt

Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.

Transmit line monitoring circuitry, and related methods, devices, and systems

Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.

Memory read masking

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Boise, ID, United States of America

Dave Jefferson