Texas Instruments Corporation

Daty Michael Rogers

Cetin Kaya

Freidoon Mehrad

Robert Kraft

Ping Jiang

Reima Tapani Laaksonen

Wei William Lee

Kenneth Joseph Newton

Men-Chee Chen

Maureen A Hanratty

Qizhi He

Guatam V Thaker

The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Antireflective structure and method

After via etch, a low-k dielectric layer ( ) is treated with an in-situ O plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.

In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning

A method of forming a floating gate memory array is provided that uses a two step etch process to prevent the formation of unwanted trenches 66 into the semiconductor substrate 26. The process may be accomplished by a first etch which is substantially not selective between silicon and dielectric materials. A second etch process is then used which is highly selective to dielectric materials.

Stack etch method for flash memory devices

A process for forming a polysilicon line having linewidths below 0.35 .mu.m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., I-line lithography). The resist pattern (40) has minimum dimensions of 0.30 .mu.m or greater. The BARC layer (30) is etched using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using an isotropic etch having a selectivity of one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below 0.3 .mu.m. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).

Polysilicon linewidth reduction using a BARC-poly etch process

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Garland, TX, United States of America

Daty Michael Rogers