Apple Inc.

Date Jan Willem Noorlag

Michael G Frank

Patrick D McNamara

Preminder Singh

Sung Wook Kang

An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC.

Compensating for aging in integrated circuits

A binning process uses curve fitting to create and assign one or more bins based on testing data of operating voltage versus leakage current for test integrated circuits. Each bin is created by assigning an initial operating voltage to the bin and fitting a curve to the testing data population. An equation is generated describing the fitted curve. Integrated circuits are binned by measuring the leakage current at a selected operating voltage and testing the integrated circuit at one or more operating voltages determined based on the fitted curves. The integrated circuits are assigned a maximum operating voltage that corresponds to the lowest tested operating voltage at which the integrated circuit passes the test.

Continuous voltage product binning

A semiconductor device is formed in which a first-type doped field effect transistor has a first gate stack that has an end portion with a second gate stack formed for a second-type, complementary doped field effect transistor. Lateral electrical contact is made between the first gate stack and the second gate stack. The lateral electrical contact provides an electrical shunt at the end of the first gate stack.

Gate stack with electrical shunt in end portion of gate stack

A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer.

PFET polysilicon layer with N-type end cap for electrical shunt

Monitoring aging information for multiple devices. Aging information of the devices may be received. Statistics regarding the multiple devices may be determined based on the aging information. For at least some of the devices, update information may be determined based on the respective aging information. The update information may include modifications to operating parameters of the devices. For example, the devices may operate according to initial parameters that are above sustainable parameters and the update information may lower the operating parameters based on the aging information.

Modifying operating parameters of a device based on aging information

Collecting information regarding electronic aging of products

In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit.

Degradation equalization for a memory

Modifying operating parameters based on device use

An aging detection circuit is disclosed. An aging detection circuit may include at least an inverter and a half-latch. During a power-up sequence, if an input voltage of the first inverter changes sufficiently to cause the output of the inverter to change states, the output of the half-latch may be set to a state indicating aging of the circuit. This indication may be used in determining whether or not a supply voltage should be changed to compensate for the aging. A first transistor of the inverter may be arranged such that it remains active subsequent to power-up of the circuit. When active, the first transistor may be subject to degradation mechanisms associated with aging and which change its threshold voltage. The threshold voltage may change such that on a successive power-ups of the circuit, the first transistor is at least momentarily deactivated, leading to the setting of the state indicating aging by the half-latch circuit.

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Fremont, CA, United States of America

Date Jan Willem Noorlag