Rockwell International Corporation

Skyworks Solutions, Inc.

Conexant Systems, Inc.

Rockwell Science Center, Inc.

Daryush Shamlou

Joseph Hubert Colles

Paul A Underbrink

Kelly H Hale

Patrick D Ryan

Guang-Ming Yin

Guangming Yin

Rajiv Gupta

Raouf Halim

Ricke Waylan Clark

Frederic M Stubbe

Edward W MacRobbie

Christian Levesque

Bo Zhang

Armond Hairapetian

Wim F Cops

Kashif A Ahmed

Bor-Rong Horng

Fritz M Rothacher

Yihai Xiang

Patrick Ryan

A system for wireless communications is provided. The system includes a hand-held wireless communications device, such as a cell phone. An antenna is connected to the cell phone. The antenna radiates radio waves over an area of less than 360 degrees of arc, such as in a cardioid or hemisphere. The antenna is oriented such that hemisphere is in the direction away from a head of a user of the cell phone.

Directional antenna for hand-held wireless communications device

Wireless communications system utilizing directional wireless communication device

A cell phone is provided that may be used with multiple radio formats, such as GSM and CDMA. The cell phone includes a receiver that receives radio signals and converts them into electrical signals. An analog to digital converter is connected to the receiver and converts an analog input to a digital output having an adjustable number of bits at an adjustable sampling frequency. A cell phone application specific integrated circuit is connected to the analog to digital converter, which is used to process the digital output to extract encoded telecommunications data in one of the supported radio formats.

Pipelined analog to digital converter

Communications systems, and particularly portable personal communications systems, such as portable phones, are becoming increasingly digital. One area that has remained largely analog, however, is the modulation and RF amplifier circuits. To produce a RF frequency waveform. An output of a class D amplifier is coupled to an integrator to create an analog signal. A resonant circuit shapes an output waveform based on the analog signal to create a sinusoidal RF broadcast signal. The waveform of the class D amplifier may be duty cycle modulated. Digital modulation may occur using a digital sigma delta modulator or a digital programmable divide modulator. Using the digital modulation techniques and class D amplification techniques together allows for broadcast a PSK signal that has been decomposed into amplitude and phase components.

Method and apparatus for producing a modulated signal

The invention discloses a system for improving performance of the RF amplification stage of communication receivers by accounting for the signal environment of the RF amplifier. The linearity, gain and power supply voltage of the RF amplification stage of the communication receiver is adjusted to produce an optimal signal into the succeeding narrow-band amplification stage(s). The adjustment of the RF stage includes mechanisms such as adjusting the RF amplifier power supply level using a DC to DC converter. It also includes allowing distortion in the RF amplification stage if the distortion in the RF amplification stage does not affect the target signal. For example, if there were a strong signal that fell within the same band as the target signal, amplification would be allowed to be so high that it distorted the undesired signals, but not the tined signals. If the desired signal is the predominant signal, within the RF amplifier's band, then the amplifier gain may be increased only to the point where distortion is detected.

System using adaptive circuitry to improve performance and provide linearity and dynamic range on demand

Modern digital integrated circuits are commonly synchronized in their workings by clock circuits. The clock frequency for a circuit must take into account the propagation delay of signals within the critical path of the circuit. If the clock time is not adequate to allow propagation of signals through the critical path, improper circuit operation may result. The propagation delay is not a constant from circuit to circuit, and even in a single circuit may change due to temperature, power supply voltage and the like. Commonly, this variation is handled by assuming a worse case propagation delay of the critical path, and then designing the clock frequency and minimum power supply voltage of the circuit so that the circuit will function under worst case conditions. However, instead of assuming a worse case propagation delay of the critical path, the propagation delay may be measured in an actual circuit path that has been constructed to be the equivalent to, or slightly worse than, the propagation delay of the critical path. By knowing the actual worst case propagation delay, the circuit may be modified to operate with lower power supply voltages, conserving power and/or to controlling the frequency of the clock, so that the clock may be operated at or near the circuit's actual, not theoretical worst case limit. Such modifications of power supply voltage and/or clock frequency may occur during circuit operation and thus, adapt the circuit to the different operating parameters of each circuit.

Critical path adaptive power control

Cellular handset with adjustable analog to digital conversion

A multiple channel signal processing circuit receives an input associated with a first channel and an input associated with a second channel. The respective inputs are sampled and processed by the circuit, which generates a sampled output signal for the first channel and a sampled output signal for the second channel. The circuit employs a shared active circuit component, such as an operational amplifier, to alternately process samples associated with the first and second channels. A network of switches are controlled by a multiphase clock signal such that the active circuit component processes samples associated with only one channel at a time; as the input for a first channel is being sampled, a previous sample for the second channel is processed. An alternate circuit embodiment may be utilized to reduce the amount of crosstalk between the channels.

Method and apparatus for multiple channel signal processing

A system for decimating a source signal with a source sample rate by a non-integer factor to a sink signal with a sink sample rate is disclosed. The system first determines a decimation factor based on a ratio of the source sample rate to the sink sample rate. The system then decimates the source signal by the decimation factor to an intermediate ('IM') signal with an IM sample rate which is larger than the sink sample rate. The IM signal is then applied to a sample-rate converter to down convert to the sink signal with the sink sample rate, using a decimation factor between only 1 and 2.

Distributed decimation sample rate conversion

A circuit for reducing switching noise caused by harmonics of an output coupled to a band of interest in a mixed signal communication device, with the mixed signal communication device having a predetermined sampling clock. The circuit comprises a bandpass delta-sigma modulator for receiving an input centered at intermediate frequency ('IF') to generate a digital output, In-phase and Quadrature-phase digital mixers for mixing the digital output from the bandpass delta-sigma modulator down to baseband digital signals, first and second digital integrators coupled to the digital mixers for integrating the baseband digital signals to generate integration outputs, first and second decimation latches coupled to the digital integrators for generating latched integration output, a programmable counter for generating jitter sampling clocks based on the predetermined sampling clock, where the jitter sampling clock has a fixed average sampling rate, first and second FIR engines coupled to the decimation latches for differentiating, low-pass filtering and droop-correcting the latched integration outputs, using the jitter sampling clocks to generate first and second filtered digital outputs.

Jitter circuit for reduced switching noise

A circuit for resetting an electronic system based on voltage fluctuations in the power supply is disclosed. The circuit comprises a diode means for generating a first voltage being offset from the supply voltage, a first inverter having its input connected to the diode and powered by a reference voltage source, a second inverter having its input connected to the same reference voltage source and powered by the power supply; and an OR- or NOR- gate having its inputs from the outputs of the first and second inverters, such that its output, when asserted, resets the electronic system.

Reduced sensitivity power-on reset circuitry

A differential amplifier with improved offset cancellation is disclosed. The differential amplifier has a floating current source coupled to the drain terminals of the differential pair for providing complementary currents to cancel the offset voltage. In this way, the tail current in the differential pair is not affected by the offset cancellation and remains constant, while the common-mode offset is not worsened by the injected current.

Offset cancellation for differential amplifiers

A converter for converting a single-ended input V.sub.IN to a differential output signal V.sub.OUT through positive and negative output terminals is disclosed. The converter comprises a fully differential amplifier with one of its input terminals coupled to the single-ended input and its other input terminal coupled to a fixed voltage. The converter also has a first resistor ('R.sub.1 ') coupled between the single-ended input and the positive input terminal of the fully differential amplifier, a second resistor ('R.sub.2 ') coupled between the fixed voltage and the negative input terminal of the fully differential amplifier, a third resistor ('R.sub.3 ') coupled between the positive input terminal and the negative output terminal of the fully differential amplifier, and a fourth resistor ('R.sub.4 ') coupled between the negative input terminal and the positive output terminal, wherein the values of such resistors are governed by: ##EQU1## The same principles can be applied to differential-to-single-ended converters as well.

Single-ended to differential converter with relaxed common-mode input

An on-board regulated voltage up-convertor for converting a first DC voltage at a first node from an electronic system to a second DC voltage for an integrated device at a second node. The convertor comprises reference generator means for generating a predetermined reference voltage at start-up, voltage regulator means coupled to said first node for regulating said first voltage at a predetermined voltage at a third node, voltage multiplier means coupled to said third node and to said second node for multiplying said predetermined voltage to generate an output voltage substantially equal to said second voltage, feedback means coupled to said second node for feeding said output voltage back to said voltage regulator means to adjust the level of said predetermined voltage at said third node according to how said output voltage is relative to said second voltage.

Efficient, well regulated, DC-DC power supply up-converter for CMOS

A circuit for converting a system supply voltage having one of two levels to a voltage for use by an integrated analog circuit connected to the system upon power-up. The circuit uses a diode-connected transistor to generate a reference voltage necessary for a regulator to regulate the supply voltage when the supply voltage is first powered up. The regulated supply voltage is doubled to a voltage level sufficient to activate the integrated analog circuit's bandgap voltage. The activated bandgap voltage is thus switched on to supply a more precise reference voltage to the regulator so that the diode-connected transistor may be de-activated to conserve power. The circuit also provides a bypass path for connecting the supply voltage directly to the integrated analog circuit when the supply voltage is the same level as the necessary voltage for the integrated analog circuit.

Growing community of inventors

Laguna Niguel, CA, United States of America

Daryush Shamlou