International Business Machines Corporation

Globalfoundries Inc.

Daryl Michael Seitzer

Albert Manhee Chu

Rohit Pradeep Shetty

Harold Pilo

Wagdi William Abadeer

George Maria Braceras

Ronald A Piro

Thomas W Wyckoff

John Atkinson Fifield

Michael Richard Ouellette

Mujahid Muhammad

Kevin William Gorman

Jonathan B Ashbrook

Jeffrey P Gambino

Steven H Voldman

Joseph Andrew Iadanza

Norman Jay Rohrer

Nazmul Habib

Douglas Willard Stout

Robert E Busch

Vinod Ramadurai

Paul T Gutwin

David A Cain

Ezra Hall

Michael Bogaczyk

Jane S Tu

A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

Read only memory (ROM) with redundancy

Various embodiments include solutions for generating a physically unclonable function. In some cases, a method includes an electronic circuit including: a static random access memory (SRAM) device having at least one memory cell with at least one transistor device therein, SRAM bias temperature instability aging circuitry coupled with the SRAM device and configured to apply aging conditions to the at least one memory cell to degrade the at least one transistor device within the at least one memory cell, and at least one computing device coupled with the SRAM device and configured to: skew a storage cell value in the at least one transistor device, measure a skewed value of the storage cell after the skewing, and create a physically unclonable function from the skewed value of the storage cell.

Methods and circuits for generating physically unclonable function

A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.

Embedded photon emission calibration (EPEC)

Aspects of the invention provide for a structure and method for determining a degree of process variation skew between a plurality of bit cells in a static random-access-memory (SRAM) column architecture. In one embodiment, a structure includes: a plurality of bit cells within a static random access memory (SRAM) column architecture; a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers; and a pre-charge circuit connected to the bit cells through the pair of multiplexers, wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells.

Process variation skew in an SRAM column architecture

Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.

Current leakage in RC ESD clamps

Aspects of the invention provide an electrostatic discharge (ESD) protection device with reduced current leakage, and a related method. In one embodiment, an ESD protection device for an integrated circuit (IC) is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp.

Reduced current leakage in RC ESD clamps

Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.

Alternate power gating enablement

An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same

The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

Method and apparatus for burn-in optimization

A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Design structure for a current control mechanism for power networks and dynamic logic keeper circuits

Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a second transistor body, respectively and (ii) a first transistor gate electrode and a second transistor gate electrode, respectively. The structure also comprises a control circuit, which is electrically coupled to the first and second transistor bodies. The structure further comprises a testing circuit, which is electrically coupled to the control circuit and the first and second transistors of the reading circuit. The testing circuit is capable of determining whether strengths of the first and second transistors are different. In response to the testing circuit determining that the strengths of the first and second transistors are different, the control circuit is capable of adjusting the voltage of the first transistor body.

Balanced sense amplifier circuits with adjustable transistor body bias

An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.

Charge modulation network for multiple power domains for silicon-on-insulator technology

A system and method is disclosed for simultaneously searching and refreshing a memory array of a dynamic content addressable memory (DCAM). According to the disclosed invention, the information stored in a row of DCAM cells being refreshed is transferred from the memory array into sense amplifiers, during a read phase of a refresh operation. A search for a matching entry can then be performed, with respect to the information that is transferred to the sense amplifiers. To determine if there is a match, search information is simultaneously compared to the information that has been transferred to the sense amplifiers and to the information that is stored in other rows of DCAM cells of said memory array. Finally, the refresh of that row is completed by restoring the information from the sense amplifiers to that row of DCAM cells.

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Essex Junction, VT, United States of America

Daryl Michael Seitzer