International Business Machines Corporation

Daryl J Kokoszka

Lee E Johnson

Steven P Larky

Paolo Sidoli

A memory apparatus includes a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and the receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, concurrently accessing at least one remaining buffer.

Method and apparatus for managing concurrent access to multiple memories

A graphics processor including an interface for providing triangle primitives representing a graphics image, a triangle interpolator coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive, a line renderer coupled to the triangle interpolator for receiving a line primitive from the triangle interpolator and for providing pixels representing the line primitive while the triangle interpolator is computing another line primitive.

High performance triangle interpolator

A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.

High performance rasterization engine

A bitblt and line draw parameter calculator for preprocessing address information for a bitblt and line draw sequencer. The sequencer computes individual pixel addresses, controls color interpolation pacing and communicates with the memory hypervisor. By partitioning memory addressing into two tasks a first line or bitblt need only be partially processed prior to starting processing on a second line or bitblt.

Method and apparatus for rendering lines

A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.

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Austin, TX, United States of America

Daryl J Kokoszka