International Business Machines Corporation

Darwin W Norton, Jr

Richard Charles Paddock

William F Detschel

Matthias Klein

Eric N Lais

Terrence K Zimmerman

Clifford T Williams

Henry R Brandt

David S Wehrly

Eric T Shalkey

Richard C Bono

Arlin E Lee

Harold F Cavagnaro

David L Silsbee

A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Input/output computer system including hardware assisted autopurge of cache entries associated with PCI address translations

An adapter for attachment to the bus or video display of a personal computer, workstation or like devices to a high performance parallel interface (HIPPI)channel of a host computer. In a system having at least three devices to be connected to a high performance parallel interface in a 'Daisy chain,' each of the devices has an adapter capable of both sending and receiving bursts of data with a data click. Each adapter includes an inbound receiver connected to the channel for receiving bursts of data and data clock and a decoder for decoding routing information contained in the bursts of data. A pass through logic circuit is connected to the decoder for interpreting the routing information. A first latch is connected to the inbound receiver for temporarily storing data bursts. A second latch is connected to the first latch for accepting data bursts when the routing information identifies a device to which the adapter is connected. A data selector is connected to the first latch for selecting data from the device or from the first latch. An outbound transmitter is connected to the channel for transmitting bursts of data and a data clock, the outbound transmitter also being connected to the data selector for transmitting data bursts to the next adapter in the Daisy chain from the first latch when the routing information does not identify the device.

High performance channel adapter having a pass through function

Adapters attach the bus or video display of a personal computer or workstation to a high performance parallel interface (HIPPI) channel of a host computer. The HIPPI channel operates at a burst rate of 100 megabytes (MB) per second. The adapter includes an electrical circuit interface to provide compatible signal levels between the HIPPI channel and the bus of the personal computer or workstation. The adapter attaching the bus includes a first-in, first-out (FIFO) buffer that receives data words from the HIPPI channel. Control logic monitors the status of the FIFO buffer and interlocks the operation of the personal computer or workstation bus with the HIPPI channel so that proper data transfer is performed by the FIFO buffer. The adapter attaching the video display includes a pair of buffers operating in a ping-pong fashion to allow data to be written while data is being read. The buffers can be addressed by the personal computer or workstation as if they were internal memory. To allow a plurality of workstations to be connected to a single HIPPI channel, the HIPPI adapter is modified to include a pass through function allowing the devices to be connected in a 'Daisy chain'.

Personal computer bus and video adapter for high performance parallel

This embodiment provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High Performance Parallel Interface (HIPPI) standard on processors complexes like the IBM 3090 having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

Computer system high speed link method and means

Growing community of inventors

Stone Ridge, NY, United States of America

Darwin W Norton, Jr