Qualcomm Incorporated

Darshan Kumar Nandanwar

Hithesh Hassan Lepaksha

Sharath Kumar Nagilla

Kartik Gunvantbhai Desai

Venkata Biswanath Devarasetty

Nirav Narendra Desai

Sagar Bamashetti

Sanku Mukherjee

Siddesh Halavarthi Math Revana

Raghava Rao M V

Arvind Garg

Linga Achuta Ram Kumar Nimmala

Nilesh Dhavlikar

Kuldeep Singh Chahal

Raghava Rao Mv

Srinivasa Kumar Munivenkata Gowda

This disclosure provides systems, methods, and devices for memory systems that support SRAM fault correction. In a first aspect, a method includes receiving, by a memory controller coupled to a memory module through a first channel and configured to store data in and access data stored in the memory module through the first channel from a host device, data to be stored in a memory of the memory module, determining, by the memory controller, a row in the memory at which the data will be stored, determining, by the memory controller based on the row, an address associated with the row, wherein the address indicates one bit location in the row at which data will not be stored, and storing, by the memory controller, the data at the row in accordance with the address, wherein the data is not stored at the one bit location.

Static random access memory (SRAM) fault correction

Apparatus and methods for maintaining approximate uniformity of aging of equivalent processing circuits in a pipeline stage(s) in a processor are disclosed. The processor includes one or more processing units that include one or more pipelines. A pipeline includes a series of pipeline stages each of which performs a particular function. In this regard, the processor also includes an age management circuit (AMC) configured to store performance factors indicative to aging of the equivalent processing circuits in a pipeline stage. In response to work input into a given pipeline stage, the AMC is further configured to route the work input to one of the equivalent processing circuits in the pipeline stage based on the stored performance factors. In so doing, the AMC controls the frequency of use of the equivalent processing circuits in its pipeline stage to substantially maintain uniform aging of the equivalent processing circuits.

Maintaining approximate uniformity of aging of equivalent processing circuits in a pipeline stage(s) in a processor

Various embodiments include methods that may be performed by a DRAM controller of a computing device for reducing power consumption in restore operations after a memory access. The method may control the memory charge restoration of a memory, by determining a time position within a refresh window of a read operation of at least one memory cell of the memory, charging the at least one memory cell to a first voltage that is based on the time position of the read operation within the refresh window; and re-charging the at least one memory cell to a full voltage upon termination of the refresh window, such that the first voltage is less than the full voltage in a first portion of the refresh window.

Refresh window aware truncation of restore voltages for random access memory

A method includes executing a first pointer authentication instruction, including a first pointer authentication code, on a pointer in a speculative path of a pipeline. The method also includes determining whether the first pointer authentication code for the pointer fails. The method further includes determining whether the first pointer authentication code for the pointer differs from a previous pointer authentication code for the pointer in response to the first pointer authentication code failing. The method still further includes incrementing a failure counter in response to determining that the first pointer authentication code for the pointer failed and that the first pointer authentication code for the pointer differs from the previous pointer authentication code for the pointer. The method additionally includes determining whether the failure counter is greater than a threshold value and performing a defensive action in response to the failure counter being greater than the threshold value.

Systems and methods for defending against side channel attacks to speculative execution of processor pipeline instructions

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

Power saving circuits to adjust frequency according to dynamic timing margin changes and adjust supply voltage to restore desired frequency and related methods

A processing unit including a dynamically allocatable vector register file for non-vector instruction processing is disclosed. The processing unit includes an integer execution circuit and integer register file for processing integer instructions. The processing unit also includes a vector execution circuit and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time. A processing unit may be called upon to execute varying workloads that vary between integer and vector operations. Rather than statically dedicating the entire vector register file to vector registers, the processor is configured to dynamically allocate a portion(s) of the vector registers in the vector register file for use in the execution of integer instructions.

Processing unit including a dynamically allocatable vector register file for non-vector instruction processing

Optimizing cache energy consumption in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a way lookup table (WLUT) circuit that is configured to receive an effective address (EA) for a memory access request. The WLUT circuit determines that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries. In response, the WLUT circuit transmits a predicted way indicator of the WLUT entry to a cache controller. The cache controller accesses, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by the predicted way indicator and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator.

Optimizing cache energy consumption in processor-based devices

A system for performing predictive run-time thermal mitigation in a processor uses at least a first temperature sensor and a first power sensor or meter to measure a junction temperature, T, value and power consumption, P, value in the processor and predicts what a temperature, TEMP, value of the processor will be in a later clock cycle of the processor based at least in part on the Tand Pvalues. If the TEMPvalue exceeds a preselected temperature threshold, TH, value, one or more thermal mitigation actions are taken to ensure that a future Tvalue measured n sample periods from the current sample period k of the processor will not exceed the THvalue.

Predictive runtime thermal management systems and methods

Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.

Methods and systems for altering the path of data movement for large-sized memory transactions

A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

Execution unit sharing between processing cores in a cluster of a system-on-chip (SoC)

A system for performing energy-efficient computing reduces the amount of data that is transferred between a processor and an external memory device. The processor and the external memory device are equipped with first and second near data processing control units (NCUs), respectively, that coordinate offloading of preselected subprocesses from the processor to a first processing circuit disposed on or near the external memory device. When the processor is performing one of these preselected processes, the first NCU transmits commands and memory addresses to the second NCU. The processing circuit on or near the memory device performs the subprocess or subprocesses and the result is forwarded by the second NCU to the first NCU, which forwards it to the processor to complete the process.

System and method for performing energy-efficient processing through reduced data movement

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Performance aware partial cache collapse

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Growing community of inventors

Bengaluru, India

Darshan Kumar Nandanwar