Kepler Computing Inc.

Darshak Doshi

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Ikenna Odinaka

Rafael Rios

Tanay Gosavi

Biswajeet Guha

Debo Olaosebikan

Pramod Kolar

Mustansir Yunus Mukadam

Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.

Time decoupled write operations for non-linear polar material based memory

A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.

Exclusive-or logic gate with non-linear input capacitors

A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.

Area oriented logic synthesis

Majority or minority logic gate with non-linear input capacitors without reset

Computer-aided design tool for minimum gate count initialization

Computer-aided design tool for gate pruning

Computer-aided design tool for inverter minimization

Computer-aided design tool for wide-input logic initialization

Computer-aided design tool for majority or minority inverter graph synthesis

Computer-aided design tool for circuit logic initialization

OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates

AND-OR-invert logic based on a mix of majority OR minority logic gate with non-linear input capacitors and other logic gates

Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits

Growing community of inventors

Sunnyvale, CA, United States of America

Darshak Doshi