International Business Machines Corporation

Darryl W Solie

Jacqueline Hegedus Wilson

Daniel Ernest Hurlimann

Ernest L Miller

James S Pogorzelski

A terminal communications circuit that provides communication through a bus interface circuit to a network bus in accordance with the predetermined communications procedure, the terminal communications circuit including a communications interchange circuit that exchanges protocol signals with the bus interface circuit in response to commands received from a signal state controller that is resident in the terminal. The communications interchange circuit further provides communications state change information to the signal state controller to indicate the contents of the protocol signals from the bus information circuit. The signal state controller executes one of a plurality of program states to control communications over the network bus in accordance with predetermined communications procedure by providing commands to the communications interchange circuit in acordance with the program state that the signal state controller is currently executing. The signal state controller changes the program state in response to the communications state change information from the communications interchange circuit. Also provided is a single command from the signal state controller to the communications interchange circuit that results in the communications interchange circuit providing a multiple of individual protocol signal patterns to the bus interface circuit enabling multiple communications procedures to be performed on the communications network with a single command from the signal state controller.

Terminal communications circuit

A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage having combinational logic connected to receive the input signals and providing the logically combined bits to latches of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter. The output of the counter is decoded to provide a signal when the counter counts to the specified number of bits in the predefined bit patterns.

Growing community of inventors

Austin, TX, United States of America

Darryl W Solie