International Business Machines Corporation

Darryl Jonathan Rumph

Bryan Keith Bullis

Michael Steven Siegel

William Robert Lee

Robert Brian Likovich, Jr

Chad Everett Winemiller

Michael Patrick Muhlada

Robert Franklin Clark

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer, and input signals from an array and a clock line providing current time. Also included is a decision block that determines which of the searches are critical and which, during peak calendar search periods, can be postponed with minimal impact to the system. The postponed searches are then conducted at a time when there is available calendar search capacity.

Apparatus and method to coordinate calendar searches in a network scheduler given limited resources

Apparatus and method that schedules movement of packets within network devices, such as network processors, includes a calendar using a segmented hierarchical routine to identify the next packet to be moved from one of a plurality of flow queues.

Configurable hardware scheduler calendar search algorithm

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices, is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

Coordination of calendar searches in a network scheduler

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array that is selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

Apparatus and method to coordinate calendar searches in a network scheduler

Apparatus and method that schedules movement of packets within network devices, such as network processors, includes a calendar using a sectored hierarchical routine to identify the next packet to be moved from one of a plurality of flow queues. The segmented hierarchical routine allows searching to begin from any starting point identified by a current pointer CP in each segment.

Apparatus, program product and method that schedules movement of packets within network devices, such as network processors, includes a time based calendar in which a segmented hierarchical routine is used to identify the calendar location of the next flow queue from which a packet is to be forwarded.

Scalable hardware scheduler time based calendar search algorithm

The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through simulation. Described is a situation in which a system has a main device through which data flows to and from other devices. Bus transfers must fall within required rates. A simulation of the configuration utilizes models of the various devices, including the &ldquo;Main device&rdquo;. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. The data rate and data validity are measured during each burst period.

System and method to independently verify the execution rate of individual tasks by a device via simulation

A method of and program for dynamically testing a buffering and selection device, wherein the buffering and selection device receives a transmission at an average bandwidth of T and in peak bandwidth bursts that may be greater than T, are provided. The buffering and selection device transmits data to one or more receive devices, all of which have a total average bandwidth of at least T. The buffering and selection device has buffers apportioned to each receive device in order to store data that is written in burst mode destined for that receive device. The method includes disabling the output data flow to the receive device being tested and then generating input data to the buffering and selection device tagged for each receive device in burst mode at a preselected number of transfers for each receive device. The program determines when the preselected number of transfers has occurred and then enables data flow to the receive device being tested. It is then determined if output to each receive device has commenced within a preselected latency period, and, if it has, it is determined if the preselected number of transfers of data has occurred within a preselected transfer period, i.e., meets bandwidth requirements.

Verifying performance of a buffering and selection network device

A multimedia display system includes a central processing unit, a storage device associated with the central processing unit, a standard interface bus to which the central processing unit and the storage device are connected, a graphics processor connected to the bus for generating graphics data in response to commands from the central processor, a digitizer for converting an analog video signal to digital form and for producing synchronization signals, a video processor for processing the digitized video data to produce pixel representations of the digitized video signal, a shared frame buffer for storing the graphics data generated by the graphics processor and the pixel representations of the video signal, a device for converting the stored digital data to a data stream appropriate for driving a video monitor, and a video monitor for displaying the graphics data and the video information, wherein the video processor generates a programmable variable phase vertical synchronization signal for synchronizing video data and graphics data through a shared frame buffer with the capacity to handle relocatable windows.

Method and apparatus for synchronizing video and graphics data in a

Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.

Growing community of inventors

Cary, NC, United States of America

Darryl Jonathan Rumph