International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Globalfoundries U.S. Inc.

Darren Lane Anand

John Atkinson Fifield

Michael Richard Ouellette

Eric D Hunt-Schroeder

John Edward Barth, Jr

Toshiaki Kirihata

Kevin William Gorman

Steven Frederick Oakland

Donald Lawrence Wheater

John Robert Goss

Peter O Jakobsen

John Matthew Safran

Gregory J Fredeman

Michael Anthony Ziegerhofer

Mark David Jacunski

Troy Joseph Perry

Alan James Leslie

Nazmul Habib

Robert J McMahon

Norman Whitelaw Robson

Thomas Gregory Sopchak

Pamela Sue Gillis

Michael A Roberge

Faraz Khan

William R Tonti

Warren Edward Maule

Luis Alfonso Lastras-Montano

Harold Pilo

Robert Brett Tremaine

Venkatraghavan Bringivijayaraghavan

Charles Arthur Kilmer

David E Lackey

Krishnan Santhana Rengarajan

Dan Moy

Dale E Pontius

Jeffrey H Dreibelbis

Krishnendu Mondal

Kevin A Batson

Larry Wissel

Douglas Wayne Kemerer

Robert Tamlyn

Steven Harley Lamphier

Bruce Cowan

Michael R Nelms

Danny Moy

Matthew C Lanahan

Thomas O Sopchak

Peter O Jacobsen

Robert Katz

Joseph F Stormes

L Owen Farnsworth, Iii

William Roy John Corbin

A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a '0' value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.

Structures and methods for deriving stable physical unclonable functions from semiconductor devices

A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage Vfor a fuse programing period or a first non-zero intermediate voltage Vfor a non-fuse programming period.

Voltage power switch

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Charge trap memory devices

The present disclosure relates to a structure including a voltage selection circuit which includes a first device and a second device, the voltage selection circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, and a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage.

Selection circuit

The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

Program and erase memory structures

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

Latching current sensing amplifier for memory array

The present disclosure relates to a structure which includes a pair of non-volatile storage devices in a memory array which are sensed to determine an initial data state and reinforced by a write operation of the initial data state to the pair of non-volatile storage devices. The structure can be used for a robust and error free physical unclonable function.

Robust and error free physical unclonable function using twin-cell charge trap transistor memory

The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

Margin test for multiple-time programmable memory (MTPM) with split wordlines

The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing

The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank.

Parallel programming of one time programmable memory array for reduced test time

Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

Voltage-aware adaptive static random access memory (SRAM) write assist circuit

A first data access request to a first row of a first memory array of the DRAM is received while a refresh operation in the first memory array is executing. The refresh operation is paused. The first data access request is executed, and simultaneously, the bits of the first row of the first memory array, including any updates indicated in the first data access request, are latched to a transfer register. The bits latched to the transfer register are written to a corresponding first row in a second memory array of the DRAM. A bank select logic is updated to indicate that subsequent data access requests to the first row in the first memory array will be executed from the second memory array. The refresh operation is then resumed.

Refresh hidden eDRAM memory

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Essex Junction, VT, United States of America

Darren Lane Anand