Intel Corporation

Darren L Abramson

Mikal Hunsaker

Michael N Derr

Khee Wooi Lee

Zohar Bogin

Karthi R Vadivelu

John S Howard

Joseph A Bennett

David I Poisner

Norman J Rasmussen

Chai Huat Gan

Brad W Hosler

Michael J McTague

Bryan C Doucette

Ioannis T Schoinas

Stephen S Pawlowski

Seh Kwa

Gary A Solomon

Su Wei Lim

Michael T Klinglesmith

Rajeev K Nalawadi

Neil W Songer

Leslie E Cline

Satheesh Chellappan

Alberto J Martinez

Jim Kardach

Raul N Gutierrez

Kar Leong Wong

Robert De Gruijl

Chang Yong Kang

C Brendan S Traw

William Knolla

Kah Meng Yeem

Adeel A Aslam

David Hines

Rajesh Raman

Jeff L Rabe

Kie Woon Lim

Adit D Tarmaster

Joe A Bennett

Kishore K Mishra

Shanthanand R Kutuva

Bret T Connell

Rob Strong

E-Liang Chew

Michael Tabet

Suryaprasad Kareenahaili

Robert DeGruijl

Raul Gutierrez

An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

Methods and apparatus to offload media streams in host devices

In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

Providing multiple roots in a semiconductor device

Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller

In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.

Providing adaptive bandwidth allocation for a fixed priority arbiter

Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests&#x2014;e.g. between those requestors providing the access requests&#x2014;the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform

A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.

Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates

Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams. When the resource buffer for the low priority stream becomes available and a corresponding request is arbitrated in the high priority arbitration pool, a grant for the request can be immediately made since grant counts for the stream already exist.

Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools

A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device.

Opportunistic initiation of data traffic

For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

Power saving for isochronous data streams in a computer system

Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools

In embodiments of the present invention, a PCI bus to PCE Express protocol conversion module includes a process implemented by control logic to convert streaming PCI information to PCI Express packets. In one embodiment, an agent may transfer PCI data and associated byte enables to a first queue, which may temporarily store the PCI data and associated byte enables in a quad word format. A decoder may determine whether the PCI byte enables are combinable, contiguous, and/or active, and, using state machines, transfer a quantity of the PCI data and associated byte enables from the first queue to a second larger queue. The state machines may break the PCI stream to arrive at the quantity of PCI data being transferred. The second queue may have at least one location to temporarily store the quantity of data and byte enables in at least one packet having a PCI express format.

PCI to PCI express protocol conversion

A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.

USB schedule prefetcher for low power

A method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule are disclosed herein. A work item is removed from an enabled expansion bus schedule data structure and a coherency signal is then generated utilizing an expansion bus host controller. The work item is then reclaimed in response to the generation of the coherency signal. In one embodiment, the enabled expansion bus schedule data structure is a Universal Serial Bus (USB) asynchronous schedule including a plurality of queue heads.

Method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule

Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

Method and apparatus for detecting an interruption in memory initialization

Growing community of inventors

Folsom, CA, United States of America

Darren L Abramson