Infineon Technologies Ag

Stmicroelectronics Gmbh

Darren Galpin

Frank Hellwig

Glenn Ashley Farrall

Sandeep Vangipuram

Ketan Dewan

Simon Cottam

Dietmar Koenig

Paul Hubbert

Trevor Bird

Shubhendu Mahajan

An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.

Interconnection of protected information between components

Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

Write busy signaling for interface structures

Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is covered by a property set. A mutatable RTL design is defined which allows for modification of a part of an RTL design from its intended behavior to a non-intended behavior, thus introducing unwanted effects. The mutatable RTL design can then be synthesized to produce a functional representation of the design. The property set can be re-run on the synthesized design to see whether the functional representation of the design is sensitive to the unwanted effect and thus whether formal verification can detect the modification.

Method of proving formal test bench fault detection coverage

A method of, and apparatus for, processing the output of a design tool for an integrated circuit, the output relating to a circuit under design. A part of the circuit to be investigated is selected. Information relating to each signal in the selected part of the signal is then selected, and an output containing the selected information for the signals in the selected part of the circuit is generated.

Method and apparatus for processing an output of a design tool

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Bristol, United Kingdom

Darren Galpin