Melexis Technologies Nv

Darrell Livezey

Volodymyr Seliuchenko

Marcelo Mizuki

Saad Ahmad

Sharath Patil

Jeannette Zarbock

Andreas Bonin

Liqun Wu

A sample-and-hold circuit is provided that includes a plurality of sample-and-hold branches arranged in parallel and each including a buffer and a sample-and-hold block including one or more sample-and-hold cells. The sample-and-hold circuit further includes a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block. The time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period.

Sample-and-hold circuit arranged for setting an adaptable time delay

A pixel circuit wherein a pixel arrangement comprises a pixel comprising a photodetector, an integrator for accumulating a signal from the photodetector, a source following output transistor for amplifying the integrated signal, and a current source for applying a readout current through the output transistor, a voltage regulating circuit comprising an amplifier, a replica transistor dimensioned substantially the same as the output transistor, and a replica current source for providing substantially the readout current through each replica transistor, a gate of the replica transistor is connected with an output node of the amplifier connected with the pixel arrangement, and a source of the replica transistor is connected with a negative input of the amplifier, and with the replica current source, a predefined reference voltage is applicable to a positive input.

Pixel voltage regulator

A sample and hold system, for capturing and reading a sequence of traces of an input signal. The sample and hold system comprising a readout device, a controller, and a sample and hold array of unit cells. The controller is configured for controlling the sample and hold system, such that during an acquisition phase a trace of samples is taken from the input signal in an original sample order and such that the samples are held in the unit cells wherein the samples are assigned to the unit cells in an acquisition order, such that during a consecutive readout phase the samples are read out from the unit cells wherein the order in which the unit cells are read out corresponds with a readout order, and such that the acquisition order and/or the readout order differs from trace to trace.

Noise reduction in sample and hold systems

A sample and hold system, for capturing and reading at least one input signal. The system comprises a readout device, a controller, an array of segments comprising a plurality of unit cells and a dummy unit cell, and segment switches between the segments and the readout device. The controller is adapted for controlling the system such that: during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells; during a readout phase the samples in the unit cells or in the dummy unit cells of a segment are read out by readout device; after opening or closing the segment switches the dummy unit cell, is the first cell which is read out by the readout device.

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Brookline, NH, United States of America

Darrell Livezey