Freescale Semiconductor,inc.

Darrell L Carder

Thomas E Tkacik

Lawrence Loren Case

Douglas Allan Hardy

Michael D Fitzsimmons

Mark D Redman

John E Spittal, Jr

Jonathan Lutz

Gregory Schmidt

Magdy Samuel Abadir

Bhoodev Kumar

Robert N Ehrlich

Milind P Padhye

Steven R Tugenberg

Rajesh Raina

Rakesh Bakhshi

Bart J Martinec

Steven Tugeberg

The present disclosure provides system and method embodiments for generation of capture clock signals. A first and second test circuit receive a first test pattern and a functional clock signal. A first test clock control (TCC) circuit of the first test circuit generates a first capture clock signal that comprises a set of functional clock signal pulses generated according to a first clock pattern of the first test pattern. A second TCC circuit of the second test circuit generates a second capture clock signal that comprises the set of functional clock signal pulses generated according to the first clock pattern. The set of functional clock signal pulses of the second capture clock signal are staggered in time from the set of functional clock signal pulses of the first capture clock signal.

Scan testing with staggered clocks

A circuit for efficiently testing digital shadow logic () in isolation from an associated non-logic design structure () includes a width and delay matched bypass circuit () coupled to receive an n-bit input from shadow logic () and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic () from the non-logic design structure () in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.

Efficient apparatus and method for testing digital shadow logic around non-logic design structures

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

Method and apparatus for secure scan testing

A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.

Testing of data retention latches in circuit devices

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Dripping Springs, TX, United States of America

Darrell L Carder