Motorola Corporation

Other

Freescale Semiconductor,inc.

Darrell Eugene Davis

Scott R Humphreys

Wayne P Shepherd

Saket Bhatia

Alan M Victor

Barry W Herold

Frederick L Martin

Raul Salvi

Cesar W Carralero

Wan F Tay

Ronald U Davis

Ankush S Bhatia

An alarm unit for monitoring or detecting presence of an analyte on a separate sensor portion. The present invention comprises only the alarm unit and its means for attachment to a user's clothing. A square plastic casing protects the alarm electronics portion including a signal processing means. A large clip attachment means is included that is easily separated and attached from the casing and is used to attach the unit to clothing and which has enough clearance to be used with thick articles of clothing including diapers and which has a set of teeth frictionally held against a rubber strip portion located on the casing back so as to also enable secure attachment to very thin articles of clothing. A three-way switch is located externally for easy alarm chime and alarm volume selection. Interdependent modes of operation enable the signal processing means to control the alarm unit operation and features including low power indication, improper cable plug installment, three-way switch deactivation during Monitor mode, and a snooze/reset feature by which the alarm is easily disabled temporarily so that, as an example, a user can focus on running to the bathroom where the device is used to treat enuresis.

Alarm unit for monitoring or detection of an analyte

In one example embodiment, an alarm unit for monitoring or detecting presence of an analyte on an analyte sensor comprises a square plastic casing protecting the alarm electronics portion and including a signal processing means, a clip attachment means configured to be separated and attached from the casing and used to attach the unit to clothing. The clip attachment has enough clearance to be used with thick articles of clothing including diapers and has a set of teeth frictionally held against a rubber strip portion located on the casing back so as to also enable secure attachment to very thin articles of clothing. The alarm unit may further comprise a three-way switch located externally for easy alarm chime and alarm volume selection. Interdependent modes of operation may enable the signal processing means to control the alarm unit operation and features including low power indication, improper cable plug installment, three-way switch deactivation during Monitor mode, and a snooze/reset feature by which the alarm is disabled temporarily so that, as an example, a user can focus on running to the bathroom where the device is used to treat enuresis.

A prescaler ( ) includes a frequency divider ( ) having an input node ( ) and a divider output ( ). The frequency divider is coupled to a clock signal and has a predetermined divisor. Series-coupled delay elements ( ) are coupled to the divider output and to the clock signal. Each delay element includes a delayed output ( ) and adds a delay equal to the clock period at the delayed output. The prescaler also includes transmission gates ( ), each transmission gate coupled between the input node and the delayed output of a corresponding one of the delay elements. When one of the transmission gates is enabled and couples the delayed output of an nth one of the delay elements to the input node, the divider output frequency equals the clock frequency divided by the predetermined divisor plus n.

Prescaler method and apparatus

A method and apparatus for constructing a temporary road bed include a mat formed from a plurality of planks having a longitudinal dimension and spaced-apart a uniform distance by a spacer. A flexible cable extends through apertures in the planks and spacers for coupling the planks and spacers together. The flexible cable allows the mat to bend and conform to the ground surface and can be rolled and folded upon itself. In one embodiment, the planks include at least one recess in a top face for interlocking with a plank of a second mat. The mats can be coupled together in an end-to-end relation to obtain a desired length or width or in a stacked relation to obtain a desired thickness of the road bed.

Temporary road bed

A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q.sub.A).

Prescaler system circuits

A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.

Suppression of noise between phase lock loops in a selective call

A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.

Frequency prescaler method and apparatus responsive to low input drive

A PLL circuit (401), including a VCO (420) having a trimming port (418) and a tuning port (416), a PLL controller (404), a variable voltage source (408), a voltage measuring circuit (426) and a multiplexer (412, 414, 428), performs automatic trimming of the VCO (420). The PLL circuit (401) accomplishes this by initiating a trimming mode that controls the multiplexer so that it couples the output of the PLL controller (404) to the trimming port (418), and the output of the variable voltage source (408) to the tuning port (416), thereby to phase lock the VCO (420) to the reference frequency signal (421). The PLL circuit (401) then measures, by way of the voltage measuring circuit (426), a voltage at the trimming port (418), switches the PLL circuit (401) to an operational mode, and then adjusts the variable voltage source (408) to be substantially equal to the voltage measured.

Automatic trimming of a controlled oscillator in a phase locked loop

A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

Fractional-N synthesizer having modulation spur compensation

A BIMOS logic gate (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (36) and provides an ECL level output signal (34). A bipolar transistor (20) is biased by a complementary ECL level input signal 32'. The other portion of the differential circuit includes a bipolar transistor (30) that is biased by an ECL level input signal 32. The emitter coupled transistors 20 and 30, receiving complementary ECL level inputs, along with the MOS transistor 36, receiving MOS level inputs, combine to provide logic functions with ECL level outputs 34 and 34'.

BIMOS logic gates

A frequency synthesizer (10) for providing a modulated output signal (fo) includes a reference frequency signal (fr) and a voltage controlled oscillator (14). For dividing the frequency of the output signal from the voltage controlled oscillator (14) by a divisor, a programmable divider (16) is coupled to the output of the voltage controlled oscillator (14). To produce a phase-locked loop in which the frequency of the output signal from the voltage controlled oscillator (14) is equal to the frequency of the reference frequency (fr) signal multiplied by the divisor, a phase detector (12 ) having a first input coupled to the reference frequency signal (fr), a second input coupled to the output of the programmable divider (16), and an output coupled to the input of the voltage controlled oscillator (14) is also provided. A first integrator (24) for integrating a modulating signal provides an integrated signal and a first control signal. Similarly, a second integrator (25) coupled to the first integrator (24) for integrating the integrated signal provides a second control signal. A differentiator ( 36, 42 and 48) coupled to the second integrator (25) differentiates the second control signal to provide a third control signal. Finally, a processor (41 and 43) coupled to the first integrator (24), the second integrator (25) and the differentiator (36, 42 and 48) processes the first, second, and third control signals and a divider modulus code (M). The processor (41 and 43) coupled to the programmable divider modifies the divider modulus code (M) in response to the modulating signal (9) to provide the divisor, whereby the frequency of the output signal from the voltage controlled oscillator (14) is modulated by the modulating signal (9).

Frequency synthesizer with FM modulation

A BIMOS lever convertor (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (32) and provides an ECL level output signal (34). The other portion of the differential circuit includes a bipolar transistor (18) that is biased by the MOS transistor (16). The bipolar transistor (18) operates to provide a complementary ECL level output signal (34') so as to provide a single ended MOS to differential ECL interface suitable for integration in an I.C.

BIMOS level convertor

A multiple conversion superheterodyne receiver system includes a first frequency synthesizer capable of generating any one of a number of predetermined first local oscillator frequencies for mixing with an incoming signal to produce a first intermediate frequency. A second frequency synthesizer selectively generates any one of two local oscillator frequencies corresponding to either high side or low side injection to be mixed with first intermediate frequency producing an appropriate second intermediate frequency. A frequency selecting circuit is operatively coupled to the first and second frequency synthesizer for selecting an appropriate one of the first local oscillator frequencies to tune the receiver to a desired channel and for selecting an appropriate one of the second local oscillator frequencies for avoiding receiver self-quieting spurious responses.

Synthesized multiple conversion receiver system with provision for

A method of programming a ROM for a multiple conversion frequency synthesizer provides a mechanism for avoiding receiver self-quieting. The method includes the steps of searching for frequencies which cause potential receiver self-quieting responses and selecting a second local oscillator frequency suitable for avoiding receiver self-quieting. A single bit of a ROM is used to represent possible second local oscillator frequencies synthesized by the frequency synthesizer which provide either high-side or low-side injection to the second mixer. Finally, the method includes the step of encoding the single second local oscillator frequency determining bit of the ROM appropriately for selecting the local oscillator frequency which avoids receiver self-quieting.

Method of programming a synthesizer ROM for elimination of receiver

A low-voltage, complementary symmetry amplifier arrangement is disclosed which functions effectively on supply voltages down to one volt DC. The amplifier is especially suited for audio processing applications in hand-held personal electronics apparatus, such as pocket radio receivers. The circuit configuration is easily implemented in integrated circuit form and operates efficiently on class B operation with its attendant advantages. The amplifier arrangement is characterized by the use of current sources in the collector and emitter circuits of a differential amplifier and thereby employs current ratios instead of the more conventional voltage levels to selectively control the conduction of associated output devices.

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Sunrise, FL, United States of America

Darrell Eugene Davis