Micron Technology Incorporated

Catalyst Semiconductor, Inc.

Micron Quantum Devices Inc.

Darrell D Rinerson

Christophe J Chevallier

Roger R Lee

Frankie F Roohparvar

Michael S Briner

Steve K Hsia

Robert D Norman

Vinod C Lakhani

Chan-Sui Pang

Asim A Bajwa

A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation. Once the memory has been fabricated and characterized, the control parameters can be selected for optimum memory performance and loaded into the data storage units.

Memory system having programmable control parameters

A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased. The positive voltage is greater in magnitude than the external primary voltage source and is preferably produced utilizing a charge pump circuit powered by the primary voltage source. The relatively large source voltage enables the cell to be erased rapidly and with a reduced tendency to produce positive charges which can be trapped in the gate oxide intermediate the floating gate and the channel/source of the cell.

Flash memory system having fast erase operation

A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline. In some embodiments, one set of wordline drivers (positioned along one side of the array) drives the even-numbered wordlines, another set of wordline drivers (positioned along the opposite side of the array) drives the odd-numbered wordlines, and the system exchanges the bitline addresses of the first packet and last packet (or the first N bytes of the first packet and the last N bytes of the last packet) of each sector to be written to cells along an even-numbered wordline (or inverts the bitline addresses for the entire sector), but the system does not modify the bitline address of any of data bit to be written to cells connected along an odd-numbered wordline. Preferably, the system is operable in either a first mode in which it modifies the addresses to which data is to be written to a cell array (to reduce the time needed to read the data after it has been written) or a second mode in which it does not modify the addresses to which the data is to be written to the array.

System and method for writing data to memory cells so as to enable

A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.

Memory circuit with pumped voltage for erase and program operations

Disclosed is a EEPROM flash memory array utilizing single transistor cells to provide read/write nonvolatile storage. The array includes a plurality of sectors, each oriented along the word line direction, and the sectors may include one or more word lines. An erase select transistor is provided for each sector and each word line includes a pass gate transistor which assists in both the programming and the erase operations.

Growing community of inventors

Cupertino, CA, United States of America

Darrell D Rinerson