Intel Corporation

Darrel K Palke

Prasoonkumar Surti

Jill MacDonald Boyce

Varghese George

Adam T Lake

Carl S Marshall

Scott R Janus

Vallabhajosyula S Somayazulu

Deepak Shashidhar Vembar

Selvakumar Panneer

Karthik Veeramani

Hugues Labbe

Mike MacPherson

Sherine Abdelhak

Zhijun Lei

Zhengmin Li

Travis T Schluessler

John G Gierach

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware.

Apparatus and method for a programmable depth stencil graphics pipeline stage

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Hillsboro, OR, United States of America

Darrel K Palke