Digital Equipment Corporation

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Digital Electric Corporation

Digital Equipment Company

Darrel D Donaldson

Richard B Gillett, Jr

Douglas D Williams

David W Hartwell

David Golden

Richard Eugene Kessler

Samuel Hammond Duncan

John M Parchem

David A Orbits

Daniel Wissell

Scott E Breach

David M Robinson

Roger A Dame

Frederick C Canter

Arvind Kumar

Mark N Howard

John Eble

Richard B Gillett Jr

Ronald E Nikel

A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a &ldquo;source&rdquo; partition and to store that information within its own &ldquo;destination&rdquo; partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover &ldquo;valid&rdquo;, but non-coherent copy of the information, e.g., a &ldquo;snapshot&rdquo; of the information as of the time of the request. Upon receiving the information, the data mover may copy it into the memory subsystem of the destination partition.

Block data mover adapted to contain faults in a partitioned multiprocessor system

The processors of a multiprocessor system are managed, or controlled, by a microprocessors referred to as MBM microprocessors, and the input/output units of the multiprocessor system are managed or controlled by microprocessors contained in PBM units. The MBM units and PBM units communicate with each other through a private local area network. The processors may be arranged into partitions by software, where the processors of a partition may exchange messages with each other, but not with other processors of the multiprocessor system. A virtual time of year clock synchronizes the microprocessors of the MBM and PBM units within a partition to form a &ldquo;base time&rdquo;. In the event that the operating system of a partition changes the time within that partition, a &ldquo;delta time&rdquo; is computed such that the base time plus the delta time gives the set time. The delta time is stored in a database which is replicated within all MBM and PBM microprocessors. A processor determines its current time by reading a register in which current time is written as partition base time plus partition delta time. An advantage of replicating the delta time of each partition in all MBM units is that all processors are then able to determine the &ldquo;current time&rdquo; of any other processor in the multiprocessor computer system, regardless of which partition the processor is in.

Method for synchronizing plurality of time of year clocks in partitioned plurality of processors where each partition having a microprocessor configured as a multiprocessor backplane manager

A control system using microprocessors for communicating through a LAN to control operation of processors and input and output subsystems (IO system) of a multi-processor computer system. Each processor includes memory, and an IO system comprising a plurality of busses. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or an IO system associated with the destination processor, etc. The processors and IO system are mounted in a rack, and an IO system is associated with each processor. A rack may be hot swapped. In hot swapping, the microprocessor control system computes new routing tables for messages through the new cabling arrangement. Microprocessors, IO devices, and processor boards may be hot swapped.

Online control of a multiprocessor computer system

A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths

An open drain driver, differential receiver circuit for transmitting logic signals generated by metal oxide semiconductor (MOS) logic circuits over a data bus that uses distributed termination impedances. The distributed termination impedance values are chosen to minimize the data bus settling time both when a driver in a given module drives a signal consisting of alternating logic levels, as well as when two different drivers drive a given logic level in succession. Each open drain driver includes a multiplexor, a flip flop, an inverter stage, and a driver transistor. The multiplexor selects either a data signal to be transmitted or a deasserted data value to be passed to the input of the flip flop. The flip flop also accepts a test input, which sets the flip flop to a known state. As a result, no additional delay is inserted in the critical path between the rising edge of a flip flop clock input signal and the driver output. The companion differential receiver receives a reference voltage which is separately generated on each module, to permit the use of distributed power supplies while still adjusting for variations which may exist in a termination voltage from module to module.

Data bus using open drain drivers and differential receivers together

A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Cache coherency protocol for multi processor computer system

A power supply interlock technique for an electronic system which uses metal oxide semiconductor (MOS) logic circuits require two or more different supply voltages, and where each circuit board module contains its own power supplies. An open-collector enable signal is both controlled and sensed by each of the modules. The enable signal is set true when all of the supplies in the system are operating properly. However, the enable signal is set false by any one of the modules if one of the higher voltage supplies on that module is malfunctioning. The enable line also controls the lower voltage power supplies in each module. None of the lower voltage power supplies is thus permitted to operate until the enable line is set true, which occurs only when all of the modules indicate they have an operating high voltage supply available. As a result, latch-up of parasitic transistors in the circuits which drive logic signals on a system bus is avoided.

Power supply interlock for a distributed power system

A node includes logic circitry for transmitting and receiving data on a backplane bus. The driver in the transmitting logic in the node acts with the current source provided by the bus to decrease the transition time of the data transmitted onto the bus. A coupling resistor is included in the node for individually coupling the driver in the node to the bus for limiting voltage excursions on the bus and providing impedance matching between the node and bus and permitting driver overlap at the bus so that higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized.

Node with coupling resistor for limiting current flow through driver

A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorites, require access to the bus.

Lookahead bus arbitration system with override of conditional access

A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Lockhead bus arbitration system with override of conditional access

A node for communicating with a plurality of other nodes in a computer, the node including logic circuitry for transmitting and receiving data at first and second logic levels. A default generator is connected to an arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

Node adapted for backplane bus with default control

A system and method for nodes to obtain access to a bus. In this arbitration method, a central arbiter selects a particular node and issues a conditional grant. The conditional grant is transmitted before it is determined whether access to the bus will actually transfer to another node. Each node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When a node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

A system for communicating between a plurality of nodes in a computer, each node including logic circuitry for transmitting and receiving data. The subject system includes (1) a backplane bus for carrying the data between the nodes, (2) a driver in each node and a current source circuit coupled to the bus which drive the bus in parallel to decrease the transition time of the data transmitted onto the bus, and (3) coupling resistors individually coupling the bus to the driver in each node and providing impedance matching between the bus and nodes and permitting driver overlap at the bus so that the higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized and resistors are used to terminate the ends of the bus to the supply voltages.

Backplane bus system including a plurality of nodes

A system for communicating between a plurality of nodes in a computer, each node including logic circuitry or transmitting and receiving data at first and second logic levels. The system includes an arbiter coupled to the nodes for detecting a lack of request activity from the nodes. A default generator is connected to the arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

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Lancaster, MA, United States of America

Darrel D Donaldson