Applied Micro Circuits Corporation

Lsi Logic Corporation

Plx Technology, Inc.

Macom Connectivity Solutions, LLC

Teranetics, Inc.

Aquantia Corporation

Applied Micro Circuts Corporations

Dariush Dabiri

Maged F Barsoum

Jose Tellado

Nitin Barot

Advait Madhav Mogre

Christopher R Keate

Tarun Gupta

Venkatesh Nagapudi

Hossein Dehghan

Ravi Bhaskaran

Dongwoon Bai

Sandeep Kumar Gupta

Nils Graef

Jing Li

Francesco Caggioni

Jinwen Xi

Moshe Malkin

Daniel A Luthi

Damien Latremouille

Gaurav Chandra

Po Tong

Ting-Yin Chen

Wenwei Pan

Qian Cheng

Shobana Swamy

Ivana Djurdjevic

A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

Concatenates of an E8 lattice with binary and non binary codes

Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.

Multi-rate transmissions over twinax cables

Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

Duplex transmission over reduced pairs of twinax cables

A transceiver architecture can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data based on a product code of an E8 lattice based on binary and non binary codes that creates an extended Hamming code of a multi-level structure of E8 with four bit estimates. During decoding the multi-level E8 decoding is performed on the Hamming code and then row decoding and column decoding are performed. Then lattice decoding is performed on the output of the row and column decoding. This decoding process can be iteratively performed a predetermined number of times until the encoded bits are decoded.

Product coded modulation scheme based on E8 lattice and binary and nonbinary codes

A transceiver architecture contains an encoder and a decoder for communicating high speed transmissions. The encoder modulates signal data based on an FEC code that has a symbol size that is not matched to a symbol size of a hexacode. Any code where the symbol size is less than the sample size for coding can be serially concatenated. During decoding the multilevel decoding leech lattice and FEC decoder iteratively passes their outputs back and forth to each other until the encoded bits are decoded.

Product coded modulation scheme based on leech lattice and binary and nonbinary codes

A transceiver architectures can comprises an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on a leech lattice. The data can be transmitted at a high speed according to the constellation with an embedded leech lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

High speed transceiver based on embedded leech lattice constellation

One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference.

Detection and estimation of narrowband interference by matrix multiplication

A transceiver architecture can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of a leech lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded leech lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

High speed transceiver based on concatenates of a leech lattice with binary and nonbinary codes

A circuit and method perform adaptive spectral enhancement at a frequency &#x3c9;(also called 'fundamental' frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal &#x3c6;(or its complement). The fundamental-enhanced signal &#x3c6;(or complement) is thereafter used in a notching circuit (also called 'fundamental notching' circuit) to generate a fundamental-notched signal y-&#x3c6;. The fundamental-notched signal y-&#x3c6;is itself enhanced to generate a harmonic-enhanced signal &#x3c6;that is used to notch the fundamental-notched signal y-&#x3c6;again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (&#x201c;cascaded-harmonic-notched&#x201d; signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency &#x3c9;. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.

Adaptive spectral enhancement and harmonic separation

A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Symmetric diagonal interleaving and encoding/decoding circuit and method

Methods and systems for multi-input IIR filters with error feedback are disclosed. By using multiple-inputs to generate multiple outputs during each iteration, a multi-input IIR filter in accordance with the present invention has greatly increased throughput. Furthermore, the addition of a multi-variable error feedback unit in accordance with the present invention in a multiple-input IIR filter can greatly increase the accuracy of the multi-variable IIR Filter.

Multi-input IIR filter with error feedback

An input signal that includes narrowband interference is spectrally enhanced by an adaptive circuit that supplies as output signal(s), portion(s) of NBI at one or more frequencies that change adaptively. The output signal(s) are used in one or more tone predictor(s) to generate, based on prior values of the NBI portion, one or more predicted tone signals that are subtracted from a received signal containing the NBI, and the result is used in the normal manner, e.g. decoded. The adaptive circuit and the one or more tone predictor(s), form a feed-forward NBI predictor wherein the received signal is supplied as the input signal of the adaptive circuit. The result of subtraction may be supplied to a slicer that slices the result, yielding a sliced signal which is subtracted from the received signal to generate a signal can be used as the input signal, to implement a feedback NBI predictor.

Adaptive narrowband interference prediction circuit and method

One or more processing units confirm existence of narrow band interference in a signal by using an estimate f of the frequency, to check for one or more harmonics. In illustrative embodiments, the estimate f is automatically identified as a second harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at either of two frequencies namely (A) frequency f/2 and (B) frequency (M&#x2212;f)/2 and whichever of these two frequencies is stronger is identified as the fundamental frequency. In several such embodiments, the estimate f is automatically identified as a third harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at any of three frequencies namely (C) frequency f/3 and (D) frequency (M&#x2212;t)/3 and (E) frequency (M+f)/3. If the predetermined criteria are not met at all five frequencies (A)-(E) then f is identified as the fundamental frequency.

Confirmation of presence of narrowband interference by harmonic analysis

A circuit and method perform adaptive spectral enhancement at a frequency &#x3c9;(also called 'fundamental' frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal &#x3c6;(or its complement). The fundamental-enhanced signal &#x3c6;(or complement) is thereafter used in a notching circuit (also called 'fundamental notching' circuit) to generate a fundamental-notched signal y&#x2212;&#x3c6;. The fundamental-notched signal y&#x2212;&#x3c6;is itself enhanced to generate a harmonic-enhanced signal &#x3c6;that is used to notch the fundamental-notched signal y&#x2212;&#x3c6;again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (&#x201c;cascaded-harmonic-notched&#x201d; signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency &#x3c9;. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.

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San Jose, CA, United States of America

Dariush Dabiri