Lightmatter, Inc.

Massachusetts Institute of Technology

Darius Bunandar

Nicholas Christopher Harris

Carl Ramey

Michael Gould

Tomo Lazovich

Mykhailo Tymchenko

Martin B Z Forsythe

Ryan Braid

Tyler J Kenney

Thomas Graham

Shashank Gupta

Carlos Dorta-Quinones

Anthony Kopa

Yemima Lorberbaum

Jon Marshall

Guy Naor

Stephanie Joanne Hamilton-Jones

Natasha Jen

Ayon Basumallik

Ajay Joshi

Sukeshwar Kannan

James Carr

Martin Forsythe

Jon Elmhurst

Binoy Shah

Bradford Turcott

Cansu Demirkiran

Eric Hein

Robert Turner

Dirk Robert Englund

Kuang C Liu

Robert A Turner

Ayon Basumalik

Clifford Chao

Nikhil Kumar

Steven Klinger

Srinivasan Ashwyn Srinivasan

Elliot Greenwald

Jessie Rosenberg

Sandeep Sane

Nicholas Dronen

David Walter

Reza Baghdadi

Nathaniel Bowman

Joseph Stadolnik, Iii

Karl C Buckenmaier

Ludmila Levkova

Lakshmi Nair

David Widemann

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Photonic communication platform and related circuits

Described herein are embodiments of a photonic computing system comprising one or more processors in communication with disaggregated memory through one or more optical channels. The disaggregated memory comprises multiple memory units placed on a photonic substrate that includes a photonic network that can be programmed to configure which of the memory units can be accessed by each of the processor(s). The disaggregated memory includes a memory controller for reading and writing data to/from the memory units. The memory controller may be configured to perform processing in concert with the processor(s).

Optical computing with disaggregated memory

Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

Systems and methods for utilizing photonic degrees of freedom in a photonic processor

Systems and methods for designing a chip configured to perform computing processes are provided. The described techniques include obtaining information associated with the chip and determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip. The chip architecture may then be generated to be used in fabrication of the chip based on the selections of the one or more circuit building blocks.

Architecting an integrated circuit or system using machine learning

Photonic communication platform and related architectures, systems and methods

Described herein are a computing systems comprising a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer, an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface.

Chiplet communication using an optical communication substrate

Described herein are techniques of training a machine learning model and performing inference using an analog processor. Some embodiments mitigate the loss in performance of a machine learning model resulting from a lower precision of an analog processor by using an adaptive block floating-point representation of numbers for the analog processor. Some embodiments mitigate the loss in performance of a machine learning model due to noise that is present when using an analog processor. The techniques involve training the machine learning model such that it is robust to noise.

Machine learning model training using an analog processor

Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel. The optical interleaver is configured to selectively couple light having wavelengths in the first wavelength set from the first waveguide bus to the I/O port, and selectively couple light having wavelengths in the second wavelength set from the I/O port to the second bus waveguide.

Spectrally interleaved optical transceivers

Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.

Photonic communication platform

Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

Fast prediction processor

Described herein are photonic communication platforms and related packages. In one example, a photonic package includes a substrate carrier having a recess formed through the top surface of the substrate carrier. The substrate carrier may be made of a ceramic laminate. A photonic substrate including a plurality of photonic modules is disposed in the recess. The photonic modules may be patterned using a common photomask, and as a result, may share a same layer pattern. A plurality of electronic dies may be positioned on top of respective photonic modules. The photonic modules enable communication among the dies in the optical domain. Power delivery substrates may be used to convey electric power from the substrate carrier to the electronic dies and to the photonic substrate. Power delivery substrates may be implemented, for example, using bridge dies or interposers (e.g., silicon or organic interposers).

Photonic wafer communication systems and related packages

A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2π radians, the photonic processor performs addition modulo 2π. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.

Residue number system in a photonic matrix accelerator

Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Systems and methods for analog computing using a linear photonic processor

Photonic communication platform and related methods for increasing yield

Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Photonics processor architecture

Growing community of inventors

Boston, MA, United States of America

Darius Bunandar