Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Stmicroelectronics Design and Application S.r.o.

Dario Livornesi

Marco Pasotti

Fabio De Santis

Roberto Bregoli

Paolo Pulici

Francesco Piscitelli

Alessio Emanuele Vergani

Vikas Rana

Sandor Petenyi

Piero Malcovati

Enrico Mammei

Michele Bartolini

Edoardo Bonizzoni

Mattia Fausto Moretti

Alessio Facen

Roberto Faravelli

Abhishek Mittal

Mojtaba Mohammadi Abdevand

According to an embodiment, a circuit includes a core and low-frequency recovery circuits. The core circuit is configured to bias a resistive sensor used to measure a fly height of a hard disk drive. The core circuit is additionally configured to amplify a high-frequency component of a sensing signal of the resistive sensor, the sensing signal indicating the fly height. The low-frequency recovery circuit is configured to amplify the sensing signal's low-frequency component.

Circuit for biasing an external resistive sensor

According to an embodiment, a circuit includes a biasing and a low-frequency recovery circuit. The biasing circuit includes a voltage digital to analog converter (V-DAC), a differential difference amplifier coupled to the V-DAC, a common-mode feedback (CMFB) amplifier coupled to the differential difference amplifier, and a first pair of transistors arranged as a high-impedance structure and coupled to the differential difference amplifier and the CMFB amplifier. The low-frequency recovery circuit includes a current digital to analog converter (C-DAC), a second pair of transistors arranged as a high-impedance structure and coupled to the first pair of transistors, a pair of resistors having a resistance value equal to half a resistance of the resistive sensor, the pair of resistors arranged between the second pair of transistors and coupled to the C-DAC, and a gain circuit coupled to shared nodes between the second pair of transistors and the pair of resistors.

An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.

Circuit and method for process and temperature compensated read voltage for non-volatile memory

A charge pump circuit has a plurality of charge pump stages cascaded to one another between an input terminal and an output terminal to provide an output voltage having a boosted value with respect to the input voltage. A clock generator is configured to generate a clock signal provided to the charge pump stages to perform the boosting of the input voltage. An output-voltage regulation feedback closed-loop is coupled to the clock generator to perform a regulation of the output voltage based on a feedback voltage. A discharge control stage is configured to control a discharge of the charge pump circuit by generating a first discharge control signal configured to disable the output-voltage regulation feedback closed-loop or a second discharge control signal configured to reduce the frequency of the clock signal.

Charge pump circuit with improved discharge and corresponding discharge method

A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

Device for generating a voltage reference comprising a non-volatile memory cell

A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node. The second capacitor includes a third plate coupled to the second storage node and having an opposite fourth plate. The second plate is coupled to the fourth plate, and the first body of the access transistor is coupled to the second body and the third body.

Non volatile memory cell and memory array

Growing community of inventors

Paderno Dugnano, Italy

Dario Livornesi