Nan Ya Technology Corporation

International Business Machines Corporation

Darin James Daudelin

Bret Roberts Dale

Ryan Andrew Jurasek

Dave Eugene Chapmen

Douglas Willard Stout

Francis H Chan

William L Bucossi

Michael J Lencioni

Adam Bertrand Wilson

Todd M Fisher

A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry. The plurality of capacitors exhibit a plurality of different capacitance values and are configured to independently turn on or off according to a plurality of inputs. Decap calibration circuitry is configured to update the plurality of inputs in response to a determination signal. A voltage detector is configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage. The decap calibration device is configured to generate the determination signal in response to the voltage comparison.

Decoupling capacitance calibration devices and methods for DRAM

A system for charging a low voltage power domain in a low power DRAM includes: a first capacitor, for providing a local domain power voltage supply; a first transistor, coupled to the first capacitor and a voltage supply and turned on by a powerdown signal, the first transistor for decoupling the first capacitor during powerdown mode, and charging the capacitor to provide the local domain power voltage supply when exiting powerdown mode; a second capacitor selectively coupled to the voltage supply or the local domain voltage power supply; and a second transistor, coupled to the second capacitor, the powerdown signal, and the local domain power voltage supply, for decoupling the second capacitor from the local domain power voltage supply during powerdown mode and coupling the second capacitor to the local domain power voltage supply when exiting powerdown mode.

System for powering up voltage domains after exiting powerdown event

A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges.

Method for detecting minimum operational frequency

A low-voltage current reference providing a current being substantially constant with temperature includes a low voltage bandgap, a start circuit coupled to the low voltage bandgap, and a current summer coupled to the low voltage bandgap and to the start circuit. The low voltage bandgap is for providing a constant voltage reference, and the start circuit is for starting the low voltage bandgap from a non-start mode and for providing a proportional to absolute temperature (PTAT) current reference. The current summer is for providing a constant current reference according to the constant voltage reference and the PTAT current reference.

Low-voltage current reference and method thereof

A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.

Power-on detection circuit for detecting minimum operational frequency

An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.

Driving circuit slew rate compensation method

A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.

Dynamic voltage pump circuit and method of dynamically generating an output supply voltage thereof

A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled by a comparison signal; a signal conversion circuit, coupled to the adjustable capacitive component, for restoring charges stored in the adjustable capacitive component to a predetermined value when a voltage level of the output signal reaches a reference value to generate a clock-like signal; and a comparison circuit, coupled to the signal conversion circuit and the adjustable capacitive component, for comparing a period of the clock-like signal with a reference period of a reference clock signal and generating the comparison signal to adjust the total capacitance of the adjustable capacitive component when periods are not the same.

System and apparatus for generating ideal rise and fall time

The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.

Electronic circuit for maintaining and controlling data bus state

A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

Apparatus for hysteresis based process compensation for CMOS receiver circuits

A driver including boost circuitry for reducing tri-state delay. Boost circuitry includes boost legs ( ) and ( ) having boost delay chains ( ) and ( ), respectively. Subcircuits ( ) and ( ) may include a series of inverters or other devices to delay a tri-state enable signal (EN ) or (EN BAR) for a predetermined amount of time substantially equivalent to the time it takes for a first signal (A ) to travel from input pin A to PAD. Transient current provides a boost by discharging or charging output nodes (G ) and (G ), respectively. Boost legs ( ) and ( ) remain on for the length of time it takes for enable signal (EN ) or (EN BAR) to travel through subcircuits ( ) and ( ). The boost increases the rate of transition of output nodes (G ) and (G ) thereby reducing the delay of tri-state signal (EN ).

Tri-state delay boost

A method and apparatus for enhancing reliability of a high voltage input/output (I/O) driver/receiver reduces voltage stress on transistors forming part of a logic I/O driver/receiver. The driver/receiver is designed to handle voltages greater than the power supply rails and a bias circuit reduces the voltage stress present on the output stage when a power supply voltage is removed from the circuit. The bias circuit is driven by I/O pin voltage to control a transistor within the I/O logic ladder.

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Williston, VT, United States of America

Darin James Daudelin