Microsoft Technology Licensing, LLC

Amazon Technologies, Inc.

Darek Josip Mihocka

Pedro Miguel Sequeira De Justo Teixeira

Martin Taillefer

Jon Robert Berry

Clarence Siu Yeen Dang

James David Cleary

Russell Charles Hadley

Jordi Mola

Juan Carlos Arevalo Baeza

Bruno C Silva

Ali-Reza Adl-Tabatabai

Pradeep Vincent

Gad Shlomo Sheaffer

Arun Upadhyaya Kishan

Jan Stephen Gray

YongKang Zhu

Pavlo Lebedynskiy

Tiansheng Tan

Bratin Saha

Burton Jordan Smith

Andrew James Edwards

Robert Geva

Peter Lachner

Vadim Bassin

Ben Niu

Ronald C Murray

Wen-Ke Chen

Richard Wurdack

Sanjay Bhansali

Ho-Yuen Chau

Kenneth Bryant Pierce

Jens Troeger

Theodore Maxwell Thomas

Ivette Carreras

Stuart D De Jong

Using a common reference address when processing calls between a native application binary interface (ABI) and a foreign ABI. Based on a caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code and that the callee is native, or a memory range not storing native code and that the callee is foreign. Execution of a callee is initiated based on one of (i) calling the callee using the reference address within an emulator when the caller is native and the callee is foreign; (ii) calling an entry thunk when the caller is foreign and the callee is native; (iii) calling an exit thunk when the caller is native and the callee is foreign; or (iv) directly calling the callee using the reference address when the caller is native and the callee is native.

Dual architecture function pointers having consistent reference addresses

A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.

Hybrid binaries supporting code stream folding

Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.

Widening memory access to an aligned address for unaligned memory operations

Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.

Native emulation compatible application binary interface for supporting emulation of foreign code

A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. When executing in a compatibility process, the EC code stream can interact with a foreign code stream that executes in an emulator. The foreign code stream can be included in the hybrid binary itself, or can be external to the hybrid binary. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.

Techniques for processing recorded program data are described. In implementations, a trace module in a computing device processes instructions of a recorded program and generates a trace file for program optimization. In implementations, the trace module records a subset of a received program for inclusion in the trace file. The computing device can also or instead be implemented to gather and initiate analysis of application data proactively and without user initiation.

Partial process recording

In aspects of arithmetic lazy flags representation for emulation, a host processor system receives application instructions that are designed for execution by a guest processor system that is different than a processor architecture of the host processor system. A host emulator receives an application instruction that includes an arithmetic operation, determines a result value of the arithmetic operation that is performed on integer values, and determines a first state variable and a second state variable. The host emulator also determines whether a subsequent application instruction will need a derivation of a subset of arithmetic flags based in part on a third state variable. The host emulator can then determine that the subsequent application instruction does not need the derivation of the subset of arithmetic flags, and perform the subsequent application instruction without a determination of the third state variable, thereby reducing processor clock cycles to emulate the application instructions.

Arithmetic lazy flags representation for emulation

Embodiments herein are directed to parallel replay of code execution. An embodiment parses trace data comprising a plurality of trace data streams that each represents execution of a corresponding one of a plurality of executable entities, and identifies a plurality of trace sections that each represents one or more events executed by one of the executable entities over a period of time. The embodiment defines an ordering among the trace sections, identifies a point of interest in at least one of the executable entities, and identifies a subset of the trace sections that, when replayed linearly according to the ordering, would encounter the point of interest. The embodiment queues the subset of trace sections in an execution pool for replay by one or more processors. Then, based on the trace data, the embodiment uses the processor(s) to replay two or more of the subset of trace sections in parallel.

Parallel replay of executable code

Augmenting a trace with at least one reverse lookup data structure during indexing of the trace. A method includes receiving trace data observed during execution of executable entit(ies), and replaying a plurality of different sections of the trace data. The replay includes, for each trace section, executing a plurality of code instructions of the executable entit(ies) based on the section's portion of the trace data, and recording attribute(s) observed during the execution of the code instructions along with an identity of the trace section. At least one reverse lookup data structure is created. It associates each of at least a subset of the attributes observed during the replay of the plurality of trace sections with the identity of each trace section in which it was observed. This reverse lookup data structure is stored as part of one or more trace data streams.

Indexing a trace by insertion of reverse lookup data structures

Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include determining that at least one of two or more hyperthreads has entered an idle state. The technique can further include executing an idle workload loop that comprises a set of instructions that substantially simulates execution of the one of the two or more hyperthreads that has entered the idle state.

CPU sharing techniques

Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

Leveraging transactional memory hardware to accelerate virtualization and emulation

Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include determining that a first thread is scheduled for execution on one of two or more hyperthreads, where the first instruction thread has a first priority. Such a technique also includes determining that a second instruction thread is one of executing or scheduled for execution on another of the two or more hyperthreads, where the second instruction thread has a second priority that is less than the first priority The technique can further include preempting execution of the second instruction thread based at least in part on the second instruction thread having the second priority that is less than the first priority.

Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.

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Mercer Island, WA, United States of America

Darek Josip Mihocka