Intel Corporation

Daqiao Du

Zhen Zhou

Kai Xiao

James A McCall

Xiang Li

Jun Liao

Ling Zheng

Zhichao Zhang

Zuoguo Wu

Kenneth Foust

Tae Young Yang

Jong-Ru Guo

Jason A Mix

Renzhi Liu

Tae-Young Yang

Anne M Sepic

Guosong Lin

Ismael Franco Núñez

Gordon P Melz

Kevin Stone

An apparatus comprising an interconnect comprising a conductive core; a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core; a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core; a first non-conductive layer between the conductive core and the first conductive layer; and a second non-conductive layer between the first conductive layer and the second conductive layer.

Electrical interconnect with improved impedance

A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

Near field wireless communication system for mother to package and package to package sideband digital communication

An apparatus is described. The apparatus includes an electro-mechanical interface having angled signal interconnects, wherein, the angling of the signal interconnects is to reduce noise coupling between the angled signal interconnects.

Packed interconnect structure with reduced cross coupled noise

A system for a three-dimensional ('3D') printed circuit board ('PCB') to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.

Printed circuit board (PCB) with three-dimensional interconnects to other printed circuit boards

Electrical interconnects having a non-linear conductive pathway, and related apparatuses and methods, are disclosed herein. In some embodiments, an electrical interconnect may include a non-linear conductive pathway electrically coupling top and bottom conductive portions. In some embodiments, an electrical interconnect may include a non-linear conductive pathway that propagates an electrical signal generating electromagnetic fields with an electrical field orthogonal to the direction of electromagnetic-wave propagation. In some embodiments, an electrical interconnect may include a non-linear conductive pathway portion and a linear conductive pathway portion. Also disclosed are connectors including an electrical interconnect having a non-linear conductive pathway. In some embodiments, a connector may include a first electrical interconnect having a non-linear conductive pathway generating first electromagnetic fields; and second electrical interconnect having a linear conductive pathway generating second electromagnetic fields that are orthogonal to the first electromagnetic fields.

Heterogeneous interconnect having linear and non-linear conductive pathways

Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.

Board integrated interconnect

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Lake Oswego, OR, United States of America

Daqiao Du