Chinese Academy of Sciences

Huawei Technologies Co., Limited

Beijing Sensetime Technology Development Co., Ltd.

University of Science and Technology Beijing

Shenzhen Sensetime Technology Co., Ltd.

Norin Mining Limited

Dapeng Chen

Huaxiang Yin

Qiuxia Xu

Chao Zhao

Wenwu Wang

Shijie Chen

Kai Han

Huilong Zhu

Tao Yang

Xiaolong Ma

Xiaolei Wang

Junfeng Li

Gaobo Xu

Changliang Qin

Jiang Yan

Jun Luo

Hongsheng Li

Huajie Zhou

Zuozhen Fu

Lingkuan Meng

Shunwan Zhuang

Huicai Zhong

Haibo Wang

Xiaogang Wang

Binbin Jiao

Wen Ou

Yixiao Ge

Fei Liu

Qingqing Liang

Liang Wang

Chao Liu

Shuai Zhang

Zhigang Li

Jinbiao Liu

Xiaobin He

Shuai Yi

Peng Ma

Jianmin Song

Tong Xiao

Honggang Liu

Shenghua Yin

Yantao Shen

Maoqing Tian

Xueli Ma

Changliang Qi

Ruiwen Liu

Yanmei Kong

Wang Wenwu

Yihong Lu

Fusong Dong

Zhanglun Song

Yunpu Qi

Jinli Du

Leiming Wang

Zhiqi Wang

A segmented grouting method for ramp drivage in an aquifer is provided. Concerning grouting reinforcement for a ramp in an aquifer, a grouting process is divided into four stages according to a pressure change, that is, micro-pressure filling, low-pressure diffusion, medium-pressure reinforcement, and high-pressure fracturing. In the micro-pressure filling, an initial pressure of a grouting orifice is 0, and a low-concentration single-component grout is used to fill an original fissure of the aquifer. In the low-pressure diffusion, a low-concentration bicomponent grout is used for grouting, the original fissure is expanded, and a grouting radius is increased. In the medium-pressure reinforcement, a high-concentration bicomponent grout is used for grouting, thereby reinforcing the aquifer. In the high-pressure fracturing, a high-concentration bicomponent grout is used to reinforce a new fractured fissure of the orifice caused by a high pressure and the original fissure, thereby forming a confining bed.

Segmented grouting method for ramp drivage in aquifer

A route processing method, a device, and a system, where the method includes: a network virtualization edge (NVE) device set including at least two NVE devices includes a common Virtual Extensible Local Area Network (VXLAN) Tunnel Endpoint (VTEP) address. The common VTEP address is used to identify a common VTEP, and the common VTEP is deployed on each NVE device in the NVE device set. In addition, each NVE device in the NVE device set includes a VTEP address, and the VTEP address is used to identify a VTEP included in a corresponding NVE device. An NVE device in the NVE device set establishes a VXLAN tunnel between the NVE devices in the NVE device set based on a VTEP address and the common VTEP address using an inclusive multicast Ethernet tag (IMET) route.

Route processing method, device, and system

The present disclosure discloses an image processing method and related device thereof. The method includes: acquiring an image to be processed; and performing a feature extraction process on the image to be processed using a target neural network so as to obtain target feature data of the image to be processed, wherein parameters of the target neural network are time average values of parameters of a first neural network which is obtained from training under supervision by a training image set and an average network, and parameters of the average network are time average values of parameters of a second neural network which is obtained from training under supervision by the training image set and the target neural network. A corresponding device is also disclosed. Feature data of image to be processed are obtained via the feature extraction process performed on the image to be processed.

Image processing method, image processing device, and storage medium

The present disclosure relates to a network optimization method and apparatus, an image processing method and apparatus, and a storage medium. The network optimization method includes: obtaining an image sample group; obtaining a first feature and a second feature of an image in the image sample group, and obtaining a first classification result by using the first feature of the image; performing feature exchange processing on an image pair in the image sample group to obtain a new image pair; obtaining a first loss value of the first classification result, a second loss value of the new image pair, and a third loss value of first features and second features of the new image pair in a preset manner; and adjusting parameters of a neural network at least according to the first loss value, the second loss value, and the third loss value until a preset requirement is met.

Network optimization method and apparatus, image processing method and apparatus, and storage medium

The present disclosure relates to an image retrieval method and apparatus. The method includes: obtaining an image group including a query image and at least one candidate image; calculating an intermediate similarity between any two images in the image group; performing multi-scale feature fusion based on the intermediate similarity between the any two images to obtain a final similarity between the query image and each candidate image; and determining a target image corresponding to the query image from each candidate image based on the final similarity. The present disclosure can improve precision and robustness of image retrieval.

Image retrieval method and apparatus

A pedestrian re-identification method includes: obtaining a target video containing a target pedestrian and at least one candidate video; encoding each target video segment in the target video and each candidate video segment in the at least one candidate segment separately; determining a score of similarity between the each target video segment and the each candidate video segment according to encoding results, the score of similarity being used for representing a degree of similarity between pedestrian features in the target video segment and the candidate video segment; and performing pedestrian re-identification on the at least one candidate video according to the score of similarity.

Pedestrian re-identification methods and apparatuses, electronic devices, and storage media

A route processing method, a device, and a system, where the method includes: a network virtualization edge (NVE) device set including at least two NVE devices includes a common Virtual Etensible Local Area Network (VXLAN) Tunnel Endpoint (VTEP) address. The common VTEP address is used to identify a common VTEP, and the common VTEP is deployed on each NVE device in the NVE device set. In addition, each NVE device in the NVE device set includes a VTEP address, and the VTEP address is used to identify a VTEP included in a corresponding NVE device. An NVE device in the NVE device set establishes a VXLAN tunnel between the NVE devices in the NVE device set based on a VTEP address and the common VTEP address using an IMET route.

A negotiation mode processing method and an intelligent network device relate to the field of communications technologies, and used to improve application flexibility of the intelligent network device. The method includes determining, by an intelligent network device, that a physical layer (PHY) receives an auto-negotiation configuration stream from a network device connected to the PHY, and changing a negotiation mode of another PHY in the intelligent network device from a non-auto-negotiation mode to an auto-negotiation mode. The auto-negotiation configuration stream indicates that the device sending the auto-negotiation configuration stream is in the auto-negotiation mode. In this way, the application flexibility of the intelligent network device can be improved, and further improves communication quality of the network device.

Negotiation mode processing method and intelligent network device

There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

Methods for manufacturing semiconductor devices

Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Method of manufacturing stacked nanowire MOS transistor

The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Semiconductor device and method of manufacturing the same

A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

Dual-metal gate CMOS devices and method for manufacturing the same

The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Semiconductor structure and method for manufacturing the same

The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

Growing community of inventors

Beijing, China

Dapeng Chen