Lsi Logic Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Ncr Corporation

Symbios Logic Inc.

Symbios, Inc.

Dao-Long Chen

Robert D Waldron

Daniel L Ellsworth

Khanh Cong Nguyen

A first-order digital PLL configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by a phase-locked loop and a local reference clock signal received by a phase-locked loop circuit. The PLL includes a data sampler which receives the incoming data stream, a frequency-locked loop (FLL) which receives the incoming data stream and is connected to the data sampler, and a frequency synthesizer which receives the local reference clock signal and is connected to the FLL. The FLL is provides a signal having a frequency which is substantially equal to the frequency of the local reference clock signal when no incoming data stream is received by the FLL, and provides a signal having a frequency which is substantially equal to the frequency of the incoming data stream when the FLL receives the incoming data stream.

Modified first-order digital PLL with frequency locking capability

The present invention discloses a novel method and apparatus for making a jitter transfer function of a phase-locked loop independent from the data transition density. The present invention is further discloses a phase-locked loop which has a loop bandwidth and a loop gain in the passband which are both independent from the received data patterns. By making the loop bandwidth independent of the received data pattern, the noise filtering performance of the phase-locked loop may be optimized.

Method to make a phase-locked loop's jitter transfer function independent of data transition density

A method of altering topology of a serial bus having a plurality of nodes interconnected in a tree topology in order to increase data rates between the plurality of nodes includes the step of obtaining a current topology representation of the serial bus which indicates a first node of the plurality of nodes is coupled to a second node of the plurality of nodes via a third node of the plurality of nodes. Another step of the method includes obtaining data rate capabilities of each node of the serial bus. The method further includes determining based upon the current topology representation of the serial bus and the data rate capabilities of each node that the third node of supports a third maximum data rate that is slower than a first maximum data rate supported by the first node and a second maximum data rate supported by the second node. Furthermore, the method includes generating in response to the determining step a new topology representation for the serial bus in which the third node is not coupled between the first node and the second node.

Method and apparatus for increasing data rates between nodes of a serial bus

A circuit and method for testing a transceiver. The circuit includes a bit pattern generator connected to the transceiver such that the bit pattern generator can communicate a serial data stream to a receiver portion of the transceiver. The circuit also includes a bit pattern checker connected to the transceiver such that a transmitter portion of the transceiver can communicate a serial data stream to the bit pattern checker. The transceiver is configured such that the receiver portion of the transceiver is communicatingly looped back to the transmitter portion of the transceiver such that a data stream can be communicated from the receiver portion of the transceiver to the transmitter portion of the transceiver. Desirably, a loopback circuit in connected to the transceiver and includes fixed bit pattern means for communicating at least one fixed bit pattern to the transmitter portion of the transceiver. The loopback circuit is configured such that the FIFO component receives a set of bits from the receiver portion of the transceiver and at least one of the bits in the set is replaced by the fixed bit pattern before being communicated to the transmitter portion of the receiver.

Method and Circuit for testing devices with serial data links

A phase interpolator that receives input clock phase and selection inputs that are distinct from the input clock phases. The phase interpolator generates an output clock phase based on the selection inputs. The phase interpolator includes selector devices which receive the input clock phases and receive the selection inputs, and includes cross-coupled switches which are connected to the selector devices and receive input clock phases therefrom. The selector devices select which input clock phases to provide to the cross-coupled switches based upon the selection inputs. The cross-coupled switches generate the output clock phase based upon the input clock phases which are received from the selector devices.

Modified phase interpolator and method to use same in high-speed, low power applications

An AC-DC voltage conversion integrate circuit that integrates all the control and protection circuits, as well as the power transistors, into a single module. Passive components, such as the transformer and capacitors, are very small, as the switching frequency is in the KHz or MHz range. Including one or more integrated switched mode power supply ICs in every wall outlet allows for providing a plurality of DC voltages from such outlets.

Wall outlet with direct current output

A circuit for detecting whether a reference clock signal, one of n phase-shifted adjacent clock signals, of a phase-locked loop (PLL) is aligned with incoming data, comprising: a data sampler for sampling bits of the incoming data with each of the adjacent clock signals, wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Also, a PLL circuit for recovering a clock signal from incoming data, comprising: a clock generator for generating an odd number, n, of phase-shifted adjacent clock signals; a data sampler for sampling the incoming data; a first pair of outputs from the sampler, for use in a phase detector (along with a reference clock of the adjacent clock signals and the incoming data), capable of producing an adjustment output. Another characterization is a method for recovering data in a PLL comprising the steps of: generating n phase-shifted adjacent clock signals for sampling bits incoming to the PLL; wherein a first of the adjacent clock signals clocks bits 0, 0+n, 0+2n, . . . , and a second of the adjacent clock signals clocks bits 1, 1+n, 1+2n, . . . . Similarly, a third of the adjacent clock signals can be used to clock bits 2, 2+n, 2+2n, . . . , as well as a fourth and fifth of the adjacent clock signals.

Data sampling and recover in a phase-locked loop (PLL)

A receiver is described for recovering digital data from a transmitted balanced signal where the balanced signal includes a first plurality of pulses, each pulse having a first pulse width. The receiver includes an input circuit, a buffer circuit, and a calibration circuit. The input circuit receives the transmitted signal and includes a first differential amplifier for amplifying a first signal, a second differential amplifier for amplifying a second signal, and a converter for receiving the amplified first signal and amplified second signal and then generating a third signal. The first and second signals are included within the transmitted signal. The buffer circuit receives and buffers the third signal, and outputs a fourth signal including a second plurality of pulses which have a second plurality of pulse widths. The calibration circuit receives the fourth signal. In response to the second plurality of pulse widths being unequal to the first pulse width, the calibration circuit generates a calibration signal. The calibration signal is received by the buffer circuit as an input. The buffer circuit utilizes the calibration signal to modify the fourth signal so that each of the second plurality of pulse widths is approximately equal to the first pulse width.

Method and system for recovering digital data from a transmitted

A method of recovering a clock signal which is embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit, first operating the data sampler circuit to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase, second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also disclosed.

Apparatus and method for recovering a clock signal which is embedded in

A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.

Single-edge triggered phase detector

A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Integral bit error rate test system for serial data communication links

A high-frequency phase locked loop circuit effectively increases the maximum frequency associated with the CMOS technology. The circuit includes a first phase-locked loop sub-circuit having an input and an output, a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop circuit and an output, and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output. The first and second phase-locked loop may be arranged in parallel or in a master/slave relationship.

High-frequency phase locked loop circuit

A clock generator circuit which produces a clock signal which may have an adjustable steady state duty cycle and which has the same frequency as a crystal frequency. The clock generator circuit includes a drive circuit coupled to the crystal which converts the first signal to a clock signal, and a duty cycle control circuit which generates a feedback signal to cause the duty cycle to automatically change to the steady state duty cycle. The clock generator circuit of the present invention may also include an output pad for allowing a measuring instrument to determine the duty cycle.

Circuit and method for generating a clock signal

A phase-locked loop design is provided that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.

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Fort Collins, CO, United States of America

Dao-Long Chen