Analog Devices International Unlimited Company

Analog Devices Global

Analog Devices Global Unlimited Company

Danzhu Lu

Bin Shao

Jie He

Langyuan Wang

Xiaohan Gong

Junxiao Chen

Brandon Day

Yihui Chen

Sean Patrick Kowalik

Suyi Yao

Alan S Walsh

A switching power converter circuit comprises a single inductive circuit element; a common control loop circuit coupled to a circuit input and the inductive circuit element and including switching circuit elements to charge the inductive circuit element using energy provided at the circuit input; at least one current sensing circuit configured to sense inductor current of the inductive circuit element; one or more output control loop circuits that each include switching circuit elements activated to generate an output voltage; and one or more pulse width modulation (PWM) circuits configured to generate a PWM control signal to activate the switching circuit elements of the output control loop circuits and to change a peak voltage of the PWM control signal of the one or more PWM circuits according to the inductor current.

Inductor current dependent pulse width modulator in a SIMO converter

Apparatus and methods for controlling voltage converter are provided. In an example, a switched-mode DC-DC voltage converter can include an inductor, at least four switches coupled to the inductor and configured to direct current through the inductor to provide a desired output voltage at an output voltage terminal of the voltage converter using an input voltage supply and a ground reference of the converter, and a controller circuit, configured to receive an indication of inductor current through the inductor and to use the slope of the inductor current to control a change between two operating modes of a group of operating modes that include a boost operating mode, a buck operating mode, and a buck-boost operating mode.

Inductor current based mode control for buck-boost converters

This disclosure describes techniques for controlling switching regulator switching operations. The techniques include selecting a given one of a plurality of clock signals based on a control signal. The techniques further include generating, by the switching regulator, an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals. The techniques further include varying the switching frequency of the switching regulator by changing a value of the control signal, used to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals that corresponds to the selected given one of the plurality of clock signals having respective values that correspond to respective ones of the plurality of refresh rate control signals.

Counter-based frequency hopping switching regulator

Techniques are provided for providing and maintaining an efficient deadtime for a switching circuit as the input voltage varies. In example, a switching circuit can include a control circuit configured to alternately switch the first switch and the second switch into and out of a low impedance state, and to prevent the first switch and the second switch from shorting the first supply rail with the second supply rail using a dead-time before a transition to the low impedance state of each of the first and second switches. The control circuit can a delay element that includes a compensation delay circuit configured to change in-kind with a change of a voltage difference between a first input supply rail and a second input supply rail of the switching circuit, and to limit a range of the dead-time over a range of the voltage difference.

Dead-time supply voltage compensation

This disclosure describes techniques for controlling switching regulator switching operations. The techniques include generating, using an inductor, a plurality of output voltage signals from an input voltage by controlling one or more switches that vary charging operations of the inductor; generating a feedback control signal based on whether the plurality of output voltage signals are within a range of target values corresponding to the plurality of output voltage signals; selecting a second output voltage signal of the plurality of output voltage signals when the feedback control signal indicates that a first output voltage signal exceeds the range of a first target value of the target values that corresponds to the first output voltage signal; and controlling the one or more switches of the switching regulator based on a difference between the selected second output voltage signal and a second target value.

Single inductor multiple output adaptive loop control

The subject disclosure includes paralleling of monolithic embedded low drop-out (LDO) linear regulator power rails to provide additional load current, while maintaining accurate current sharing and balancing between the paralleled LDOs without additional power consumption for different load current requirements. Lossless current sensing is used to sense the current for each channel. An offset generator compares the voltages for a master channel and one or more slave channels, and generates an offset voltage according to the sensed error. The offset voltage is added between an input reference voltage and an output regulated voltage to cancel the offset of each channel, so the current of each channel is substantially the same. The lossless current sensing can be realized with equivalent series resistance compensation or current limit sensing. The offset generator can be realized with a resistor and current mirror topology or an input pair added to an error amplifier input.

Lossless current balancing and sharing between paralleled linear voltage regulators

An electronic circuit includes parallel linear regulator circuits that support a range of different load currents. The electronic circuit includes a first linear regulator circuit coupled to an output node, a second linear regulator circuit coupled in parallel with the first linear regulator circuit and the output node, and a control circuit. The control circuit is configured to monitor the output node and to suppress or inhibit the second linear regulator circuit from supplying the output node when a representation of load power consumption is below a specified threshold. The first linear regulator circuit is configured to continue to supply a portion of the load power when the representation of load power consumption is above the specified threshold, and the control circuit may disable the second linear regulator circuit when the representation of load power consumption is below the specified threshold.

Load-dependent control of parallel regulators

This application discusses techniques for reducing the energy of an output ripple in a voltage converter at a switching frequency of the voltage converter. In certain examples, an amplitude of a reference voltage can be modulated with a time-varying random value or pseudo-random value to provide a reduction in the energy of the output ripple at the switching frequency of the voltage converter.

Noise reduction in a voltage converter

Techniques for indicating a load level of a DC-DC switching converter are provided. IN an example, a method for real-time load current detection for a switching converter using a discontinuous conduction mode (DCM) of operation can include generating a minimum DCM current threshold based on an reference current source and a duty cycle of the switching converter, receiving a representation of inductor charge current from power switch of the switching converter at a comparator, comparing the representation to the DCM current threshold, and controlling the power switch using a discontinuous conduction mode of the switching converter when a peak of the representation exceeds the minimum DCM current threshold.

Load current detection techniques for discontinuous conduction mode

An active voltage divider circuit is provided comprising: a first node; a second node; a third node; multiple FET load devices coupled in series between the first node and the second node; multiple first switches, each associated with a different FET load device and configured to selectably couple a respective associated bypass circuit between source and drain of its associated FET load device; and second switch circuitry configured to selectably couple a drain of a FET load device, from among the multiple FET load devices, to the third node.

Active device divider circuit with adjustable IQ

A device to detect an electrical signal is provided. The device includes sensing, output, and pull-down nodes. The device includes a pull-down circuit having a native metal-oxide-semiconductor field-effect transistor (MOSFET) to pull down the output node to approximately a voltage of the pull-down node. The device includes a switch circuit having a junction field-effect transistor (JFET). The JFET turns on the pull-down circuit in response to a voltage of the sensing node being less than a first threshold. The JFET also turns off the pull-down circuit in response to the voltage of the sensing node being greater than the first threshold.

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Shanghai, China

Danzhu Lu