Texas Instruments Corporation

Inventchip Technology Co., Ltd.

Fairchild Semiconductor Corporation

Shanghai Zhuanxin Corporation Management Consulting Partnership

Danyang Zhu

Zhong Ye

Jie Feng

Ball Fan

Xiaonan Wang

Zhuang Ma

Frank Tang

Kening Gao

Lei Huang

Honglin Guo

Myron J Miske

Xiong Li

Zhong Yu Chen

Lin Sheng

Zhidong Liu

Abha Singh Kasper

Xinyu Yin

Steven Bolen

Albert Eardley

Sheng Lin

William Toth

Michael Dean Shilhanek

An apparatus includes a capacitor coupled to a gate of a power switch, and a negative voltage adjustment device connected to a common node of the capacitor and the gate of the power switch, wherein the negative voltage adjustment device is configured such that after a turn-off signal is applied to the gate of the power switch, a voltage across the capacitor is maintained at a predetermined voltage level through a negative current provided by the negative voltage adjustment device.

Power switch drive circuit and device

An apparatus includes a capacitor coupled to a power switch, wherein the capacitor is configured to provide a negative gate voltage to the power switch when a turn-off signal is applied to a gate of the power switch, and a sink and source power supply coupled to the capacitor, wherein the sink and source power supply has a first current limit for controlling a sink current flowing from the capacitor to the sink and source power supply, and a second current limit for controlling a source current flowing from the sink and source power supply to the capacitor.

Gate leakage current monitor apparatus and control method

The invention relates to the field of power semiconductor devices. This invention discloses a drive circuit and device of a power switch. The input terminal of the drive circuit receives a pulse signal; the output terminal of the drive circuit is connected to a capacitor circuit. The capacitor circuit is used to provide a negative voltage for a first electrode of the power switch to turn off the power switch when the pulse signal is a turn-off signal; the drive circuit includes a capacitance adjustment unit. The capacitance adjustment unit includes a negative voltage adjustment element that can charge a capacitor whose voltage is lower than a predetermined voltage when the pulse signal is the turn-off signal.

A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.

Device with isolation barrier and fault detection

An isolation device provides high common mode transient immunity without increasing the supply voltage rails in the transmitter side. In one aspect, the disclosed isolation device implements a self-boosting scheme to increase a voltage swing of a transmission signal under a lesser supply voltage rail. The disclosed isolation device includes a first stage circuit, a boost circuit, and a second stage circuit. The first stage circuit is configured to generate first and second signals each having a first voltage within a supply voltage range. The boost circuit is configured to provide a boosted voltage range greater than the supply voltage range responsive to at least one of the first or second signal. The second stage circuit is configured to generate an output signal based on either one of the first or second signal, such that the output signal has a second voltage within the boosted voltage range.

Self-boost isolation device

An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is configured to provide a ground potential. The plurality of bi-directional pins are configured to provide a differential input signal for the integrated circuit. The electro-static discharge (ESD) clamp is coupled between the ground potential and the plurality of bi-directional pins.

Method and circuitry for on-chip electro-static discharge protection scheme for low cost gate driver integrated circuit

A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

High voltage level shifter with short propagation delay

A method includes comparing, by a voltage-second (VS) controller, a first duty cycle used to control a first switch at a primary side of a power transformer of a DC-to-DC converter with a threshold. The method further includes if a value of the first duty cycle is less than the threshold, controlling, by the VS controller, a second duty cycle used to control a second switch at a secondary side of the power transformer, and maintaining a voltage level at an output voltage node at a non-zero value, and if the value of the first duty cycle is greater than the threshold, controlling, by an output voltage loop, the second duty cycle based on the first duty cycle, and monotonically increasing the voltage level the at the output voltage node from the non-zero value to a predetermined value.

Pre-bias startup of a converter

A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P), a second input pin (P), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.

Multi-channel MCM with test circuitry for inter-die bond wire checking

An embodiment of a bidirectional signal interface includes first and second nodes and first and second translating circuits. The first and second nodes are respectively operable to receive a first logic signal and a second logic signal. The first translating circuit has a first signal path coupled between the first and second nodes, is operable to sense a transition of the first logic signal on the first node, and, in response to the transition, is operable to couple the first logic signal to the second node via the first signal path. The second translating circuit has a second signal path that is coupled between the first and second nodes and that is parallel to the first signal path, is operable to sense a transition of the second logic signal on the second node, and is, in response to the transition of the second logic signal, operable to couple the second logic signal to the first node via the second signal path.

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Beijing, China

Danyang Zhu