Shenzhen Microbt Electronics Technology Co., Ltd.

Danyang Wang

Zuoxing Yang

Zhijun Fan

Yun Zhai

Shuangyan Chen

Tianzhi Xue

The present disclosure relates to a multiplier, a multiply-accumulate circuit, an operational circuit, a processor, and a calculation apparatus. The operational circuit includes an input processing circuit and the multiply-accumulate circuit. The input processing circuit receives a first number and outputs the first number as a first multiplicator for feeding into the multiply accumulate circuit by negating a sign bit of the first number in a case in which the first number is a signed number, and directly outputs the first number as the first multiplicator for feeding into the multiply-accumulate circuit in a case in which the first number is an unsigned number. The input processing circuit further receives a previously known second number and directly outputs the second number as a second multiplicator for feeding into the multiply-accumulate circuit. The multiply-accumulate circuit includes a multiplication subcircuit and an accumulation subcircuit.

Multiplier, multiply-accumulate circuit, operational circuit, processor, and calculation apparatus

The present disclosure relates to a multiplier, a multiply-accumulate circuit, and a convolution operation unit. The multiplier includes: one or more selection circuits, each of the one or more selection circuits respectively configured to select a target preset multiple of a first operand from a preset multiple of a first operand as a fourth operand according to a corresponding third operand, wherein the target preset multiple is equal to a value of the third operand; and a partial product summing circuit, each of one or more input terminals of the partial product summing circuit respectively connected to an output terminal of corresponding one of at least one or more selection circuits, wherein the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits.

Multiplier, multiply-accumulate circuit, and convolution operation unit

This disclosure relates to a divider, a processor, and a calculation apparatus. The divider includes: a first-stage shift circuit, configured to shift a received first operand to left to generate a second operand; a first-stage selection circuit, configured to select a first preset multiple of a third operand as a fourth operand from preset multiples of the third operand; and a first-stage operational circuit, configured to calculate an OR operation result of the first preset multiple and a difference between the second operand and the fourth operand as a fifth operand.

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Guangdong, China

Danyang Wang