Atmel Corporation

Hefei Reliance Memory Limited

Artemis Acquisition LLC

Danut Manea

Yongliang Wang

Richard V De Caro

Lorenzo Bedarida

Stephen Trinh

Andrea Sacco

Jeffrey P Kotowski

Mirella Marsella

Jeff Kotowski

Paul Hill

Scott N Fritz

Dixie Nguyen

Erwin Castillon

Uday Mudumba

Sabina Centazzo

Richard V Caro

Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.

Voltage-mode bit line precharge for random-access memory cells

A self-setting/resetting latch circuit is disclosed that includes resistive loads for inverters used for setting and clearing the latch. In a first embodiment, the resistive loads cause the latch circuit to automatically set in response to a power supply voltage going low. In an alternate embodiment, the latch circuit is configured to be self-resetting or self-clearing when the power supply voltage goes low by reversing the set and clear terminals of the latch circuit and selecting a different node to be the output terminal of the latch circuit. The disclosed latch circuit is small and robust and draws zero power in the set state.

Self-setting/resetting latch

Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device, determining an estimated baud rate of the host device based on the transition, and communicating with the host device based on the estimated baud rate. Determining the estimated baud rate can include charging a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sampling a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjusting the charging rate based on a comparison between the capacitor voltage and a reference voltage.

Single-wire communications using iterative baud learning

In a bandgap voltage reference with low package shift, a proportional to absolute temperature (PTAT) voltage is generated using a single diode biased at two different current levels at two different times. Using the same diode for both current density measurements removes the absolute value of the base-emitter junction voltage (Vbe) and any package shift in the PTAT voltage. The bandgap voltage reference can be implemented in a single or differential circuit topology. In some implementations, the bandgap voltage reference can include circuitry for curvature correction.

Voltage reference with low sensitivty to package shift

Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device; determining an estimated baud rate of the host device based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and communicating with the host device based on the estimated baud rate.

A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

Ultra-deep power-down mode for memory devices

Voltage reference with low sensitivity to package shift

Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.

Adaptive programming for non-volatile memory devices

This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

Method and system to access memory

A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.

Fast dynamic low-voltage current mirror with compensated error

A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate of the first p-channel transistor, and a drain; a first n-channel MOS transistor having a source coupled to ground, and a gate and a drain coupled to the drain of the second p-channel transistor; a zero-threshold n-channel MOS transistor having a drain coupled to a current-output node, a gate coupled to the gate of the first n-channel transistor, and a source; and a second n-channel MOS transistor having a source coupled to ground, and a gate coupled to the gate of the first n-channel transistor and a drain coupled to the source of the zero-threshold n-channel transistor.

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Saratoga, CA, United States of America

Danut Manea