Texas Instruments Corporation

Dialog Semiconductor (uk) Limited

Dantes John

Visvesvaraya Appala Pentakota

Nitin Kumar Agarwal

Ramesh Kumar Singh

Supreet Joshi

Aditya Polepeddi

Stefano Rachiele

A method for determining one or more tests suitable for verifying that a circuit conforms to a specification is presented. The specification has at least one state machine. Example circuits are asynchronous circuits. The method includes analysing the specification to automatically determine the one or more tests for circuit verification.

Methods relating to circuit verification

Methods and systems for synchronizing a slave device with a master device are disclosed. The method includes arranging a bitstream of data into a two-dimensional frame having a plurality of columns and rows. The method further includes searching the columns for an occurrence of an 8-bit static sync word having a constant sync value. The total number of columns of the two-dimensional frame is equal to the number of columns of a group containing the 8-bit static sync word. The method also includes re-aligning the two-dimensional frame by shifting and re-numbering the column having the 8-bit static sync word to column zero. The method also includes determining the number of rows of the re-aligned frame and synchronizing the slave device with the master device based on the re-aligned frame and the number of columns and rows of the two-dimensional frame.

Methods and systems for synchronization of slave device with master device

An offset correction circuit examines a residue signal of a stage of a pipeline analog to digital converter (ADC) to determine whether a parameter which could cause offset error, needs to be adjusted. In an embodiment, the parameter is adjusted until a maximum range of the residue signal equals an expected range. In the described examples, the adjusted parameters include timing offset error (when components of an ADC sample the input signal at different time instances) and a voltage offset error (the threshold voltage at which a sub-ADC in a stage the generated sub-code changes to a next value).

Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters

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Munich, Germany

Dantes John