General Electric Company

Silicon Power Corporation

Dante E Piccone

Victor A Temple

Boris Reshetnyak

Istvan Somos

Donald E Castleberry

Ahmad Nadeem Ishaque

Henri M Rougeot

Peter Menditto

Homer H Glascock, Ii

Constantine A Neugebauer

Harold F Webster

Donald M Demarest

Robert E Hysell

David Leonard Mueller

Fadel A Selim

Angelo L DeCecco

Harshad Mehta

Leroy B Major

James E McIntyre, Deceased

Thomas R Peterson

A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Matrix stages solid state ultrafast switch

A circuit for turning OFF a thyristor. The circuit includes at least one first circuit element configured to provide a high reverse turn-OFF voltage to the thyristor gate for a predetermined period of time. Immediately following the predetermined period of time, at least one second circuit element provides a normal reverse turn-OFF voltage to the thyristor gate. The normal reverse turn-OFF voltage is substantially lower than the high reverse turn-OFF voltage.

Device and method for controlling the turn-off of a solid state switch (SGTO)

Matrix-stages solid state ultrafast switch

This high-power semiconductor device comprises (a) a disk of refractory metal having flat faces at its opposite sides and (b) two wafers of a semiconductor material having a coefficient of expansion similar to that of the refractory metal, the wafers being alloyed to the faces of the refractory metal disk in substantially aligned relationship to each other to form an assembly of the wafer and the disk with alloyed joints between the wafers and the disk. The alloyed joints are formed at elevated temperatures, and the wafers are of such size and thickness that the tendency of the wafer at one side of the disk to cause bowing of the assembly upon cooling of the assembly following formation of the alloyed joints is counteracted by a substantially equal and opposite tendency of the wafer at the opposite side of the disk to produce a substantially equal and opposite amount of bowing of the assembly, thereby resulting in a substantially flat assembly of the wafers and the disk upon cooling of the assembly following formation of the alloyed joints. The refractory metal disk is of tungsten or molybdenum, has a diameter of at least 11/2 inches, and has a thickness of at least 5 mils and of such thickness value that if the wafer at one side of the disk were omitted so that a single wafer disk was present, the single wafer assembly would be subject to substantial bowing when it cooled following formation of the alloyed joint between the disk and the remaining wafer. A method of making this device is also claimed.

High power semiconductor device and method of making same

The power thyristor of this invention has a cellular emitter structure. Each cell also has a FET assisted turn-on gate integrated into the cell. A turn-on gate voltage of one polarity is applied to a FET gate element that overlies the surface of the cell and to the turn-on gate integrated into the cell. When this voltage is so applied, a channel underlying the FET gate element becomes conductive, which allows the integrated turn-on gate to provide drive to the upper base-upper emitter junction of the thyristor cell thereby turning the thyristor cell on.

Power thyristor with MOS gated turn-off and MOS-assised turn-on

A method of forming a planar semiconductor device, such as an array of APDs, includes the steps of doping a substantially planar block of n type semiconductor material with a p type dopant in accordance with a selected pattern to form a plurality of n type wells in the block surrounded by a foundation of p type semiconductor material. Each n type well is disposed so as to respectively adjoin a first surface of the block and such that a respective p-n junction is formed between the n type material in the well and the p type material foundation. The n type semiconductor material in each well has a substantially constant concentration of n type dopant throughout the n type material; the concentration of p type dopant in the foundation has a positive gradient extending from the p-n junction towards the second surface such that the peak surface electric field of the p-n junction in each well is less than the bulk electric field of the same p-n junction.

Method for fabrication of deep-diffused avalanche photodiode

This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is 'on'. The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer. A gate electrode in ohmic contact with the gate layer in said predetermined surface regions of the gate layer surrounds the PN subjunctions between said fingers and said gate layer. The main current-carrying portion further comprises a cathode electrode having portions respectively registering with and in ohmic contact with the cathode-layer fingers.

MOS-controlled high-power thyristor

Deep-diffused planar avalanche photodiode

This GTO thyristor comprises: (i) a cathode layer that is divided into a large number of cathode-layer fingers, (ii) a gate layer contiguous with the fingers, with a PN junction J1 between each finger and the gate layer, (iii) a cathode electrode on each finger, and (iv) a gate electrode on the gate layer having portions surrounding the fingers disposed in spaced relation to the fingers. Turn-off of the GTO thyristor is effected by forcing a turn-off current to flow between the cathode electrode of each finger and the gate electrode through the associated PN junction J1. This PN junction at each finger has a centrally-located region that is characterized by an avalanche voltage that is substantially lower than the avalanche voltage that characterizes this junction in the region of the junction surrounding the centrally-located region, and this relatively lower avalanche voltage enhances the current turn-off capabilities of the GTO thyristor.

High current gate turn-off thyristor

A hermetically sealed package for a power semiconductor wafer is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap and base, each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown between the cap and base. An arc suppressant is disposed within the package between the semiconductor wafer edge and the sidewall for preventing electrical arcing between the base and cap.

Silicon packages for power semiconductor devices

A field terminated diode device includes contiguous anode, base, and cathode regions, which are respectively P+, N-, and N+ semiconductor material. The N- base region includes therein a grid region of P type semiconductor material. The grid region includes grid openings which define channels in the grid region for communicating charge carriers between the anode and cathode regions. Means are provided for electrically connecting to the anode and cathode regions and to the grid region. In one embodiment, the grid channels are nonuniform in that their average widths increase from the center to the perimeter of the device. In another embodiment, the nonuniform channels are distributed throughout the grid region.

Semiconductor device with variable grid openings for controlling

An overvoltage responsive triggering circuit for a main high power thyristor comprises a plurality of n auxiliary thyristors and electric energy storing means connected in series across said main thyristor. The auxiliary thyristors are poled to conduct forward current in the same direction as said main thyristor and have an aggregate forward breakdown voltage greater than a predetermined threshold magnitude. Said threshold magnitude is greater than the aggregate forward voltage of said n auxiliary thyristors minus the forward breakdown voltage of one of said auxiliary thyristors. Between the anode and another electrode of said one auxiliary thyristor there is connected secondary voltage breakdown means having a blocking voltage less than the forward breakdown voltage of said one auxiliary thyristor, whereby said triggering circuit becomes conductive in the breakdown mode at said threshold voltage magnitude.

Adjustable overvoltage protected circuit for high power thyristors

A circuit for triggering a silicon controlled rectifier (SCR) when the voltage across the SCR has a predetermined polarity and exceeds a predetermined magnitude. The anode of a zener diode is connected to the SCR cathode and a resistor is connected between the SCR anode and the zener diode cathode. The voltage at the zener diode cathode acts as a bias for the trigger signal. A silicon unilateral switch responds to the biased trigger signal to trigger the SCR into the conductive state when the biased trigger signal level exceeds the switching voltage of the silicon unilateral switch.

Thyristor trigger circuit enabled by thyristor forward voltage level

A circuit for controlling the reverse recovery current in a controlled rectifier. The primary winding of a saturable reactor is connected in series with the controlled rectifier. A diode in parallel with a resistor is connected in circuit with the secondary winding of the saturable reactor. The diode is poled to provide a low impedance in the reactor secondary when current flows through the primary winding and through the forward direction of the controlled rectifier. The reverse recovery current of the controlled rectifier flowing through the primary winding of the reactor causes current in the secondary winding to flow in the reverse direction of the diode. The value of the resistor as reflected into the saturable reactor primary circuit limits the magnitude of the reverse recovery current.

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Glenmoore, PA, United States of America

Dante E Piccone