Xilinx, Inc.

Danny Tsung-Heng Wu

Roger D Flateau, Jr

Boon Yong Ang

Jason J Moore

James D Wesselkamper

Steven E McNeil

Edward S Peterson

David Tran

An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

Mixed storage of data fields

Some examples herein provide for protection of data on a data path in a memory system in an integrated circuit. In an example, an integrated circuit includes a bit checker circuit, an Error Correcting Code (ECC) encoder circuit, an ECC decoder circuit, and a check bit generation circuit. The bit checker circuit is configured to check write data based on write-path check bit(s). The ECC encoder circuit is configured to generate a write encoded ECC value based on the write data. The write encoded ECC value is to be written to the memory with the write data. The ECC decoder circuit is configured to decode a read encoded ECC value and check read data based on the read encoded ECC value. The read encoded ECC value and read data are read from the memory. The check bit generation circuit is configured to generate read-path check bit(s) from the read data.

Protection of data on a data path in a memory system

A device includes a processor, an SBI, and a plurality of interfaces. The processor is configured to manage operations of the device. The SBI is coupled to the processor. The plurality of interfaces is associated with the SBI. The interfaces of the plurality of interfaces have different interface protocol from one another. The SBI is configured by the processor and the configuration of the SBI activates one interface of the plurality of interfaces at any given time. The active interface that is selected from the plurality of interfaces and a host have a same interface protocol. The active interface is configured to receive host data from the host. The SBI is configured to generate a flag for the processor in response to the active interface receiving the host data. The SBI is configured to transmit device data to the host.

Bridge supporting multiple interfaces access to subsystem

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San Jose, CA, United States of America

Danny Tsung-Heng Wu