Motorola Corporation

Danny P Shum

Ko-Min Chang

Kuo-Tung Chang

Craig T Swift

Frank Kelsey Baker, Jr

Thomas Jew

Juan Buxo

William J Taylor

Yun-Kang (Kevin) K Wu

A non-volatile memory cell (,) includes a drain-side select transistor (,), a source-side select transistor (,), and a storage transistor (,). The drain-side select transistor (,) is adjacent to the drain of the storage transistor (,) to prevent drain-disturb events. The source-side select transistor (,) is adjacent to the source of the storage transistor (,) to prevent source-disturb events. The select gate (,) of the drain-side select transistor (,), the select gate (,) of the source-side select transistor (,), and the floating gate (,) of the storage transistor (,) are formed on a dielectric layer (,) having a uniform thickness.

Non-volatile memory cell and method for manufacturing same

An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).

Semiconductor device memory cell and method for selectively erasing the

An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.

Method for making an EEPROM cell with isolation transistor

A process for fabricating a non-volatile memory cell (10) in a semiconductor device includes the formation of a doped region (28) in a semiconductor substrate (40) underlying a floating gate electrode (16) and separated therefrom by a tunnel dielectric layer (44). Stress induced failure of the tunnel dielectric layer (44) is avoided by laterally diffusing dopant atoms under the floating gate electrode (16) after completely fabricating both the floating gate electrode (16) and the underlying tunnel dielectric layer (44).

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Austin, TX, United States of America

Danny P Shum